powerpc: Move the testing of CPU_FTR_COHERENT_ICACHE into __flush_icache_range
authorKevin Hao <haokexin@gmail.com>
Tue, 6 Aug 2013 10:23:30 +0000 (18:23 +0800)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Wed, 14 Aug 2013 04:56:06 +0000 (14:56 +1000)
In function flush_icache_range(), we use cpu_has_feature() to test
the feature bit of CPU_FTR_COHERENT_ICACHE. But this seems not optimal
for two reasons:
 a) For ppc32, the function __flush_icache_range() already do this
    check with the macro END_FTR_SECTION_IFSET.
 b) Compare with the cpu_has_feature(), the method of using macro
    END_FTR_SECTION_IFSET will not introduce any runtime overhead.

[And while at it, add the missing required isync] -- BenH

Signed-off-by: Kevin Hao <haokexin@gmail.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
arch/powerpc/include/asm/cacheflush.h
arch/powerpc/kernel/misc_32.S
arch/powerpc/kernel/misc_64.S

index b843e35122e8934d7ea902e71ef0cae36f670611..60b620d64ac9b3e7bc22c87f007059fd5ae8cf64 100644 (file)
@@ -35,8 +35,7 @@ extern void __flush_disable_L1(void);
 extern void __flush_icache_range(unsigned long, unsigned long);
 static inline void flush_icache_range(unsigned long start, unsigned long stop)
 {
-       if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
-               __flush_icache_range(start, stop);
+       __flush_icache_range(start, stop);
 }
 
 extern void flush_icache_user_range(struct vm_area_struct *vma,
index e469f30e6eeb88b4668e11a86d287e99b67aeae2..1722a2be66ca7116e16e7e55e16fabd43937f0f9 100644 (file)
@@ -329,6 +329,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
  */
 _KPROBE(__flush_icache_range)
 BEGIN_FTR_SECTION
+       isync
        blr                             /* for 601, do nothing */
 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
        li      r5,L1_CACHE_BYTES-1
index 6820e45f557b73b848fda82c512332752b760dc2..74d87f11756635c429bfd26f62d79565c9241227 100644 (file)
@@ -68,7 +68,9 @@ PPC64_CACHES:
  */
 
 _KPROBE(__flush_icache_range)
-
+BEGIN_FTR_SECTION
+       blr
+END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 /*
  * Flush the data cache to memory 
  *