OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
omap2_control_base_init();
omap2xxx_check_revision();
- omap2xxx_prm_init();
+ omap2_prcm_base_init();
omap2xxx_cm_init();
omap2xxx_voltagedomains_init();
omap242x_powerdomains_init();
OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
omap2_control_base_init();
omap2xxx_check_revision();
- omap2xxx_prm_init();
+ omap2_prcm_base_init();
omap2xxx_cm_init();
omap2xxx_voltagedomains_init();
omap243x_powerdomains_init();
omap2_control_base_init();
omap3xxx_check_revision();
omap3xxx_check_features();
- omap3xxx_prm_init();
+ omap2_prcm_base_init();
+ omap3xxx_prm_init(NULL);
omap3xxx_cm_init();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
omap2_control_base_init();
omap3xxx_check_revision();
ti81xx_check_features();
- am33xx_prm_init();
+ omap2_prcm_base_init();
am33xx_cm_init();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
omap2_control_base_init();
omap3xxx_check_revision();
ti81xx_check_features();
- am33xx_prm_init();
+ omap2_prcm_base_init();
am33xx_cm_init();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
omap2_control_base_init();
omap3xxx_check_revision();
am33xx_check_features();
- am33xx_prm_init();
+ omap2_prcm_base_init();
am33xx_cm_init();
am33xx_powerdomains_init();
am33xx_clockdomains_init();
omap2_control_base_init();
omap3xxx_check_revision();
am33xx_check_features();
- omap44xx_prm_init();
+ omap2_prcm_base_init();
omap4_cm_init();
am43xx_powerdomains_init();
am43xx_clockdomains_init();
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
omap4xxx_check_revision();
omap4xxx_check_features();
- omap44xx_prm_init();
+ omap2_prcm_base_init();
omap4_cm_init();
omap4_pm_init_early();
omap44xx_voltagedomains_init();
OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
omap4_pm_init_early();
- omap44xx_prm_init();
+ omap2_prcm_base_init();
omap5xxx_check_revision();
omap4_cm_init();
omap54xx_voltagedomains_init();
OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
omap4_pm_init_early();
- omap44xx_prm_init();
+ omap2_prcm_base_init();
dra7xxx_check_revision();
omap4_cm_init();
dra7xx_powerdomains_init();
* @mem: IO mem pointer for this module
* @offset: module base address offset from the IO base
* @flags: PRCM module init flags
+ * @init: low level PRCM init function for this module
+ * @np: device node for this PRCM module
*/
struct omap_prcm_init_data {
int index;
void __iomem *mem;
s16 offset;
u16 flags;
+ int (*init)(const struct omap_prcm_init_data *data);
+ struct device_node *np;
};
extern void omap_prcm_irq_cleanup(void);
extern void omap2_set_globals_prm(void __iomem *prm);
int omap_prcm_init(void);
int omap2_prm_base_init(void);
+int omap2_prcm_base_init(void);
# endif
/*
.clear_mod_irqs = &omap2xxx_prm_clear_mod_irqs,
};
-int __init omap2xxx_prm_init(void)
+int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data)
{
- omap2_prm_base_init();
return prm_register(&omap2xxx_prm_ll_data);
}
extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
-extern int __init omap2xxx_prm_init(void);
+int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data);
#endif
.reset_system = am33xx_prm_global_warm_sw_reset,
};
-int __init am33xx_prm_init(void)
+int __init am33xx_prm_init(const struct omap_prcm_init_data *data)
{
- omap2_prm_base_init();
return prm_register(&am33xx_prm_ll_data);
}
#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
#ifndef __ASSEMBLER__
-int am33xx_prm_init(void);
+int am33xx_prm_init(const struct omap_prcm_init_data *data);
#endif /* ASSEMBLER */
#endif
.vp_clear_txdone = &omap3_prm_vp_clear_txdone,
};
-int __init omap3xxx_prm_init(void)
+int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data)
{
omap2_clk_legacy_provider_init(TI_CLKM_PRM,
prm_base + OMAP3430_IVA2_MOD);
- omap2_prm_base_init();
-
if (omap3_has_io_wakeup())
prm_features |= PRM_HAS_IO_WAKEUP;
extern void omap3_prm_vcvp_write(u32 val, u8 offset);
extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
-extern int __init omap3xxx_prm_init(void);
+int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data);
void omap3xxx_prm_iva_idle(void);
void omap3_prm_reset_modem(void);
int omap3xxx_prm_clear_global_cold_reset(void);
.vp_clear_txdone = omap4_prm_vp_clear_txdone,
};
-int __init omap44xx_prm_init(void)
+int __init omap44xx_prm_init(const struct omap_prcm_init_data *data)
{
- omap2_prm_base_init();
omap_prm_base_init();
if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx())
#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
#include "prm44xx_54xx.h"
-#include "prcm-common.h"
#include "prm.h"
#define OMAP4430_PRM_BASE 0x4a306000
#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
+#include "prcm-common.h"
+
/* Function prototypes */
#ifndef __ASSEMBLER__
extern void omap4_prm_vcvp_write(u32 val, u8 offset);
extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
-extern int __init omap44xx_prm_init(void);
+int __init omap44xx_prm_init(const struct omap_prcm_init_data *data);
#endif
#define __ARCH_ARM_MACH_OMAP2_PRM54XX_H
#include "prm44xx_54xx.h"
-#include "prcm-common.h"
#include "prm.h"
#define OMAP54XX_PRM_BASE 0x4ae06000
#ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM7XX_H
-#include "prm44xx_54xx.h"
#include "prcm-common.h"
+#include "prm44xx_54xx.h"
#include "prm.h"
#define DRA7XX_PRM_BASE 0x4ae06000
#include "prm2xxx_3xxx.h"
#include "prm2xxx.h"
#include "prm3xxx.h"
+#include "prm33xx.h"
#include "prm44xx.h"
#include "common.h"
#include "clock.h"
return 0;
}
-static struct omap_prcm_init_data prm_data = {
+#ifdef CONFIG_ARCH_OMAP2
+static struct omap_prcm_init_data omap2_prm_data __initdata = {
.index = TI_CLKM_PRM,
+ .init = omap2xxx_prm_init,
};
+#endif
-static struct omap_prcm_init_data omap3_prm_data = {
+#ifdef CONFIG_ARCH_OMAP3
+static struct omap_prcm_init_data omap3_prm_data __initdata = {
.index = TI_CLKM_PRM,
+ .init = omap3xxx_prm_init,
/*
* IVA2 offset is a negative value, must offset the prm_base
*/
.offset = -OMAP3430_IVA2_MOD,
};
+#endif
-static struct omap_prcm_init_data scrm_data = {
- .index = TI_CLKM_SCRM,
+#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_TI81XX)
+static struct omap_prcm_init_data am3_prm_data __initdata = {
+ .index = TI_CLKM_PRM,
+ .init = am33xx_prm_init,
+};
+#endif
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+ defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
+static struct omap_prcm_init_data omap4_prm_data __initdata = {
+ .index = TI_CLKM_PRM,
+ .init = omap44xx_prm_init,
};
+#endif
-static const struct of_device_id omap_prcm_dt_match_table[] = {
- { .compatible = "ti,am3-prcm", .data = &prm_data },
- { .compatible = "ti,am4-prcm", .data = &prm_data },
- { .compatible = "ti,dm814-prcm", .data = &prm_data },
- { .compatible = "ti,dm816-prcm", .data = &prm_data },
- { .compatible = "ti,omap2-prcm", .data = &prm_data },
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
+static struct omap_prcm_init_data scrm_data __initdata = {
+ .index = TI_CLKM_SCRM,
+};
+#endif
+
+static const struct of_device_id omap_prcm_dt_match_table[] __initconst = {
+#ifdef CONFIG_SOC_AM33XX
+ { .compatible = "ti,am3-prcm", .data = &am3_prm_data },
+#endif
+#ifdef CONFIG_SOC_AM43XX
+ { .compatible = "ti,am4-prcm", .data = &omap4_prm_data },
+#endif
+#ifdef CONFIG_SOC_TI81XX
+ { .compatible = "ti,dm814-prcm", .data = &am3_prm_data },
+ { .compatible = "ti,dm816-prcm", .data = &am3_prm_data },
+#endif
+#ifdef CONFIG_ARCH_OMAP2
+ { .compatible = "ti,omap2-prcm", .data = &omap2_prm_data },
+#endif
+#ifdef CONFIG_ARCH_OMAP3
{ .compatible = "ti,omap3-prm", .data = &omap3_prm_data },
- { .compatible = "ti,omap4-prm", .data = &prm_data },
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+ { .compatible = "ti,omap4-prm", .data = &omap4_prm_data },
{ .compatible = "ti,omap4-scrm", .data = &scrm_data },
- { .compatible = "ti,omap5-prm", .data = &prm_data },
+#endif
+#ifdef CONFIG_SOC_OMAP5
+ { .compatible = "ti,omap5-prm", .data = &omap4_prm_data },
{ .compatible = "ti,omap5-scrm", .data = &scrm_data },
- { .compatible = "ti,dra7-prm", .data = &prm_data },
+#endif
+#ifdef CONFIG_SOC_DRA7XX
+ { .compatible = "ti,dra7-prm", .data = &omap4_prm_data },
+#endif
{ }
};
prm_base = mem + data->offset;
data->mem = mem;
+
+ data->np = np;
+
+ if (data->init)
+ data->init(data);
}
return 0;
}
+int __init omap2_prcm_base_init(void)
+{
+ return omap2_prm_base_init();
+}
+
/**
* omap_prcm_init - low level init for the PRCM drivers
*