drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 23 May 2014 15:30:19 +0000 (21:00 +0530)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 11 Jun 2014 14:57:28 +0000 (16:57 +0200)
CHV uses the gen8 shadow register mechanism so we shouldn't be
checking the GT FIFO status.

This effectively removes the posting read, so add an explicit
posting read using FORCEWAKE_ACK_VLV (which is what use in
vlv_forcewake_reset()).

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_uncore.c

index bc18444da7869a3d9350a3a9e0871397a7d98325..871c2841af04b2550215aedc674fdd5bd924af7d 100644 (file)
@@ -250,9 +250,10 @@ static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
                __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
                                _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 
-       /* The below doubles as a POSTING_READ */
-       gen6_gt_check_fifodbg(dev_priv);
-
+       /* something from same cacheline, but !FORCEWAKE_VLV */
+       __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
+       if (!IS_CHERRYVIEW(dev_priv->dev))
+               gen6_gt_check_fifodbg(dev_priv);
 }
 
 static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)