i40e: only enable PTP interrupt cause if PTP is enabled
authorJacob Keller <jacob.e.keller@intel.com>
Sun, 14 Dec 2014 01:55:08 +0000 (01:55 +0000)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Fri, 16 Jan 2015 11:56:53 +0000 (03:56 -0800)
We should not blindly enable the PTP interrupt flags for all PFs. We
should only enable the PTP interrupt in PFs which have enabled
PTP.

Change-ID: I051a17cae4c199a2f3cf7852266e27eda6630525
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
drivers/net/ethernet/intel/i40e/i40e_main.c

index c3a353dd524e3d027aacaf15f4e756a3a8ea25d4..0cc02665a8e32908bdd02ce718d8663c77afce07 100644 (file)
@@ -2819,8 +2819,9 @@ static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
  * i40e_enable_misc_int_causes - enable the non-queue interrupts
  * @hw: ptr to the hardware info
  **/
-static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
+static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
 {
+       struct i40e_hw *hw = &pf->hw;
        u32 val;
 
        /* clear things first */
@@ -2832,11 +2833,13 @@ static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
              I40E_PFINT_ICR0_ENA_GRST_MASK          |
              I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
              I40E_PFINT_ICR0_ENA_GPIO_MASK          |
-             I40E_PFINT_ICR0_ENA_TIMESYNC_MASK      |
              I40E_PFINT_ICR0_ENA_HMC_ERR_MASK       |
              I40E_PFINT_ICR0_ENA_VFLR_MASK          |
              I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
 
+       if (pf->flags & I40E_FLAG_PTP)
+               val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
+
        wr32(hw, I40E_PFINT_ICR0_ENA, val);
 
        /* SW_ITR_IDX = 0, but don't change INTENA */
@@ -2866,7 +2869,7 @@ static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
        q_vector->tx.latency_range = I40E_LOW_LATENCY;
        wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
 
-       i40e_enable_misc_int_causes(hw);
+       i40e_enable_misc_int_causes(pf);
 
        /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
        wr32(hw, I40E_PFINT_LNKLST0, 0);
@@ -7137,7 +7140,7 @@ static int i40e_setup_misc_vector(struct i40e_pf *pf)
                }
        }
 
-       i40e_enable_misc_int_causes(hw);
+       i40e_enable_misc_int_causes(pf);
 
        /* associate no queues to the misc vector */
        wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);