nouveau_display.o nouveau_connector.o nouveau_fbcon.o \
nouveau_hdmi.o nouveau_dp.o \
nouveau_pm.o nouveau_volt.o nouveau_perf.o nouveau_temp.o \
- nouveau_mxm.o \
+ nouveau_mxm.o nouveau_agp.o \
nouveau_abi16.o \
nouveau_bios.o \
nv04_fence.o nv10_fence.o nv84_fence.o nvc0_fence.o \
--- /dev/null
+#include <linux/module.h>
+
+#include "drmP.h"
+#include "drm.h"
+
+#include "nouveau_drv.h"
+#include "nouveau_agp.h"
+
+#if __OS_HAS_AGP
+MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)");
+static int nouveau_agpmode = -1;
+module_param_named(agpmode, nouveau_agpmode, int, 0400);
+
+static unsigned long
+get_agp_mode(struct drm_device *dev, unsigned long mode)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+
+ /*
+ * FW seems to be broken on nv18, it makes the card lock up
+ * randomly.
+ */
+ if (dev_priv->chipset == 0x18)
+ mode &= ~PCI_AGP_COMMAND_FW;
+
+ /*
+ * AGP mode set in the command line.
+ */
+ if (nouveau_agpmode > 0) {
+ bool agpv3 = mode & 0x8;
+ int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode;
+
+ mode = (mode & ~0x7) | (rate & 0x7);
+ }
+
+ return mode;
+}
+
+static bool
+nouveau_agp_enabled(struct drm_device *dev)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+
+ if (!drm_pci_device_is_agp(dev) || !dev->agp)
+ return false;
+
+ switch (dev_priv->gart_info.type) {
+ case NOUVEAU_GART_NONE:
+ if (!nouveau_agpmode)
+ return false;
+ break;
+ case NOUVEAU_GART_AGP:
+ break;
+ default:
+ return false;
+ }
+
+ return true;
+}
+#endif
+
+void
+nouveau_agp_reset(struct drm_device *dev)
+{
+#if __OS_HAS_AGP
+ u32 save[2];
+ int ret;
+
+ if (!nouveau_agp_enabled(dev))
+ return;
+
+ /* First of all, disable fast writes, otherwise if it's
+ * already enabled in the AGP bridge and we disable the card's
+ * AGP controller we might be locking ourselves out of it. */
+ if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
+ dev->agp->mode) & PCI_AGP_COMMAND_FW) {
+ struct drm_agp_info info;
+ struct drm_agp_mode mode;
+
+ ret = drm_agp_info(dev, &info);
+ if (ret)
+ return;
+
+ mode.mode = get_agp_mode(dev, info.mode);
+ mode.mode &= ~PCI_AGP_COMMAND_FW;
+
+ ret = drm_agp_enable(dev, mode);
+ if (ret)
+ return;
+ }
+
+
+ /* clear busmaster bit, and disable AGP */
+ save[0] = nv_mask(dev, NV04_PBUS_PCI_NV_1, 0x00000004, 0x00000000);
+ nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
+
+ /* reset PGRAPH, PFIFO and PTIMER */
+ save[1] = nv_mask(dev, 0x000200, 0x00011100, 0x00000000);
+ nv_mask(dev, 0x000200, 0x00011100, save[1]);
+
+ /* and restore bustmaster bit (gives effect of resetting AGP) */
+ nv_wr32(dev, NV04_PBUS_PCI_NV_1, save[0]);
+#endif
+}
+
+void
+nouveau_agp_init(struct drm_device *dev)
+{
+#if __OS_HAS_AGP
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct drm_agp_info info;
+ struct drm_agp_mode mode;
+ int ret;
+
+ if (!nouveau_agp_enabled(dev))
+ return;
+
+ ret = drm_agp_acquire(dev);
+ if (ret) {
+ NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
+ return;
+ }
+
+ ret = drm_agp_info(dev, &info);
+ if (ret) {
+ NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
+ return;
+ }
+
+ /* see agp.h for the AGPSTAT_* modes available */
+ mode.mode = get_agp_mode(dev, info.mode);
+
+ ret = drm_agp_enable(dev, mode);
+ if (ret) {
+ NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
+ return;
+ }
+
+ dev_priv->gart_info.type = NOUVEAU_GART_AGP;
+ dev_priv->gart_info.aper_base = info.aperture_base;
+ dev_priv->gart_info.aper_size = info.aperture_size;
+#endif
+}
+
+void
+nouveau_agp_fini(struct drm_device *dev)
+{
+#if __OS_HAS_AGP
+ if (dev->agp && dev->agp->acquired)
+ drm_agp_release(dev);
+#endif
+}
--- /dev/null
+#ifndef __NOUVEAU_AGP_H__
+#define __NOUVEAU_AGP_H__
+
+void nouveau_agp_reset(struct drm_device *);
+void nouveau_agp_init(struct drm_device *);
+void nouveau_agp_fini(struct drm_device *);
+
+#endif
#include "drm.h"
#include "drm_crtc_helper.h"
#include "nouveau_drv.h"
+#include "nouveau_agp.h"
#include "nouveau_abi16.h"
#include "nouveau_hw.h"
#include "nouveau_fb.h"
#include "drm_pciids.h"
-MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)");
-int nouveau_agpmode = -1;
-module_param_named(agpmode, nouveau_agpmode, int, 0400);
-
MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
int nouveau_modeset = -1;
module_param_named(modeset, nouveau_modeset, int, 0400);
goto out_abort;
}
+ nouveau_agp_fini(dev);
+
NV_INFO(dev, "And we're gone!\n");
pci_save_state(pdev);
if (pm_state.event == PM_EVENT_SUSPEND) {
pci_set_master(dev->pdev);
/* Make sure the AGP controller is in a consistent state */
- if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
- nouveau_mem_reset_agp(dev);
+ nouveau_agp_reset(dev);
/* Make the CRTCs accessible */
engine->display.early_init(dev);
if (ret)
return ret;
- if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
- ret = nouveau_mem_init_agp(dev);
- if (ret) {
- NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
- return ret;
- }
- }
+ nouveau_agp_init(dev);
NV_INFO(dev, "Restoring GPU objects...\n");
nouveau_gpuobj_resume(dev);
/* nouveau_drv.c */
extern int nouveau_modeset;
-extern int nouveau_agpmode;
extern int nouveau_duallink;
extern int nouveau_uscript_lvds;
extern int nouveau_uscript_tmds;
extern void nouveau_mem_vram_fini(struct drm_device *);
extern int nouveau_mem_gart_init(struct drm_device *);
extern void nouveau_mem_gart_fini(struct drm_device *);
-extern int nouveau_mem_init_agp(struct drm_device *);
-extern int nouveau_mem_reset_agp(struct drm_device *);
extern void nouveau_mem_close(struct drm_device *);
extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq,
#include "drm_sarea.h"
#include "nouveau_drv.h"
+#include "nouveau_agp.h"
#include "nouveau_pm.h"
#include <core/mm.h>
#include <subdev/vm.h>
nouveau_mem_gart_fini(struct drm_device *dev)
{
nouveau_sgdma_takedown(dev);
-
- if (drm_core_has_AGP(dev) && dev->agp) {
- struct drm_agp_mem *entry, *tempe;
-
- /* Remove AGP resources, but leave dev->agp
- intact until drv_cleanup is called. */
- list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
- if (entry->bound)
- drm_unbind_agp(entry->memory);
- drm_free_agp(entry->memory, entry->pages);
- kfree(entry);
- }
- INIT_LIST_HEAD(&dev->agp->memory);
-
- if (dev->agp->acquired)
- drm_agp_release(dev);
-
- dev->agp->acquired = 0;
- dev->agp->enabled = 0;
- }
+ nouveau_agp_fini(dev);
}
bool
return false;
}
-#if __OS_HAS_AGP
-static unsigned long
-get_agp_mode(struct drm_device *dev, unsigned long mode)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
-
- /*
- * FW seems to be broken on nv18, it makes the card lock up
- * randomly.
- */
- if (dev_priv->chipset == 0x18)
- mode &= ~PCI_AGP_COMMAND_FW;
-
- /*
- * AGP mode set in the command line.
- */
- if (nouveau_agpmode > 0) {
- bool agpv3 = mode & 0x8;
- int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode;
-
- mode = (mode & ~0x7) | (rate & 0x7);
- }
-
- return mode;
-}
-#endif
-
-int
-nouveau_mem_reset_agp(struct drm_device *dev)
-{
-#if __OS_HAS_AGP
- uint32_t saved_pci_nv_1, pmc_enable;
- int ret;
-
- /* First of all, disable fast writes, otherwise if it's
- * already enabled in the AGP bridge and we disable the card's
- * AGP controller we might be locking ourselves out of it. */
- if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
- dev->agp->mode) & PCI_AGP_COMMAND_FW) {
- struct drm_agp_info info;
- struct drm_agp_mode mode;
-
- ret = drm_agp_info(dev, &info);
- if (ret)
- return ret;
-
- mode.mode = get_agp_mode(dev, info.mode) & ~PCI_AGP_COMMAND_FW;
- ret = drm_agp_enable(dev, mode);
- if (ret)
- return ret;
- }
-
- saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
-
- /* clear busmaster bit */
- nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
- /* disable AGP */
- nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
-
- /* power cycle pgraph, if enabled */
- pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
- if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
- nv_wr32(dev, NV03_PMC_ENABLE,
- pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
- nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
- NV_PMC_ENABLE_PGRAPH);
- }
-
- /* and restore (gives effect of resetting AGP) */
- nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
-#endif
-
- return 0;
-}
-
-int
-nouveau_mem_init_agp(struct drm_device *dev)
-{
-#if __OS_HAS_AGP
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct drm_agp_info info;
- struct drm_agp_mode mode;
- int ret;
-
- if (!dev->agp->acquired) {
- ret = drm_agp_acquire(dev);
- if (ret) {
- NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
- return ret;
- }
- }
-
- nouveau_mem_reset_agp(dev);
-
- ret = drm_agp_info(dev, &info);
- if (ret) {
- NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
- return ret;
- }
-
- /* see agp.h for the AGPSTAT_* modes available */
- mode.mode = get_agp_mode(dev, info.mode);
- ret = drm_agp_enable(dev, mode);
- if (ret) {
- NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
- return ret;
- }
-
- dev_priv->gart_info.type = NOUVEAU_GART_AGP;
- dev_priv->gart_info.aper_base = info.aperture_base;
- dev_priv->gart_info.aper_size = info.aperture_size;
-#endif
- return 0;
-}
-
static const struct vram_types {
int value;
const char *name;
struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
int ret;
- dev_priv->gart_info.type = NOUVEAU_GART_NONE;
-
-#if !defined(__powerpc__) && !defined(__ia64__)
- if (drm_pci_device_is_agp(dev) && dev->agp && nouveau_agpmode) {
- ret = nouveau_mem_init_agp(dev);
- if (ret)
- NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
- }
-#endif
+ nouveau_agp_init(dev);
if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
ret = nouveau_sgdma_init(dev);
#include "nouveau_drv.h"
#include "nouveau_drm.h"
+#include "nouveau_agp.h"
#include "nouveau_fbcon.h"
#include <core/ramht.h>
#include <subdev/gpio.h>
spin_lock_init(&dev_priv->context_switch_lock);
spin_lock_init(&dev_priv->vm_lock);
+ /* Make sure the AGP controller is in a consistent state */
+ nouveau_agp_reset(dev);
+
/* Make the CRTCs and I2C buses accessible */
ret = engine->display.early_init(dev);
if (ret)
projects / GitHub / MotorolaMobilityLLC / kernel-slsi.git / commitdiff