clk: tegra: Add sor_safe clock

The sor_safe clock is a fixed factor (1:17) clock derived from pll_p. It
has a gate bit in the peripheral clock registers. While the SOR is being
powered up, sor_safe can be used as the source until the SOR brick can
generate its own clock.

Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index fe6c6afcfa60b93257d6ecf4d7459730422324d3..36c974916d4fb73ffb7dbcc57e57eb739392fc80 100644 (file)
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -307,6 +307,7 @@ enum clk_id {
        tegra_clk_xusb_ss_div2,
        tegra_clk_xusb_ssp_src,
        tegra_clk_sclk_mux,
+       tegra_clk_sor_safe,
        tegra_clk_max,
 };
 

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 8133f92361fcc1a951bc6cc009128775aa897ae5..6f661717e593420035bd890cda0d8f0a809e5f6c 100644 (file)
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2470,6 +2470,10 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
                                              1, 17, 207);
        clks[TEGRA210_CLK_DPAUX1] = clk;
 
+       clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
+                                             1, 17, 222);
+       clks[TEGRA210_CLK_SOR_SAFE] = clk;
+
        /* pll_d_dsi_out */
        clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
                                clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);