drm/i915/skl: Use a LRI for WaDisableDgMirrorFixInHalfSliceChicken5

I have no idea how that crept in, but we need to do the write from the
ring and this is a masked register. Two fixes in 1!

Cc: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ab8ce4ceed2e4efaa43d6a2ebf17ab0a9c48ff18..e758c059267569120fa6c2fdd996904783fc8154 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -959,13 +959,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 
        if (INTEL_REVID(dev) == SKL_REVID_A0 ||
            INTEL_REVID(dev) == SKL_REVID_B0) {
-               /*
-               * WaDisableDgMirrorFixInHalfSliceChicken5:skl
-               * This is a pre-production w/a.
-               */
-               I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,
-                       I915_READ(GEN9_HALF_SLICE_CHICKEN5) &
-                       ~GEN9_DG_MIRROR_FIX_ENABLE);
+               /* WaDisableDgMirrorFixInHalfSliceChicken5:skl */
+               WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
+                                 GEN9_DG_MIRROR_FIX_ENABLE);
        }
 
        if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) {