drm/amdgpu/gfx6: add ring callbacks for ib and dma frame size
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 16 Sep 2016 14:56:33 +0000 (10:56 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 16 Sep 2016 19:52:55 +0000 (15:52 -0400)
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

index e7293f64d9530d458ea2d3516bf86e1ac0ae4d1d..410b29c05671809f11da50eda1642c1528a536d4 100644 (file)
@@ -2685,6 +2685,33 @@ static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
        amdgpu_ring_write(ring, 0);
 }
 
+static unsigned gfx_v6_0_ring_get_emit_ib_size(struct amdgpu_ring *ring)
+{
+       return
+               6; /* gfx_v6_0_ring_emit_ib */
+}
+
+static unsigned gfx_v6_0_ring_get_dma_frame_size_gfx(struct amdgpu_ring *ring)
+{
+       return
+               5 + /* gfx_v6_0_ring_emit_hdp_flush */
+               5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
+               14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
+               7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
+               17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
+               3; /* gfx_v6_ring_emit_cntxcntl */
+}
+
+static unsigned gfx_v6_0_ring_get_dma_frame_size_compute(struct amdgpu_ring *ring)
+{
+       return
+               5 + /* gfx_v6_0_ring_emit_hdp_flush */
+               5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
+               7 + /* gfx_v6_0_ring_emit_pipeline_sync */
+               17 + /* gfx_v6_0_ring_emit_vm_flush */
+               14 + 14 + 14; /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
+}
+
 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
        .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
        .select_se_sh = &gfx_v6_0_select_se_sh,
@@ -3113,6 +3140,8 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
        .test_ib = gfx_v6_0_ring_test_ib,
        .insert_nop = amdgpu_ring_insert_nop,
        .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
+       .get_emit_ib_size = gfx_v6_0_ring_get_emit_ib_size,
+       .get_dma_frame_size = gfx_v6_0_ring_get_dma_frame_size_gfx,
 };
 
 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
@@ -3129,6 +3158,8 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
        .test_ring = gfx_v6_0_ring_test_ring,
        .test_ib = gfx_v6_0_ring_test_ib,
        .insert_nop = amdgpu_ring_insert_nop,
+       .get_emit_ib_size = gfx_v6_0_ring_get_emit_ib_size,
+       .get_dma_frame_size = gfx_v6_0_ring_get_dma_frame_size_compute,
 };
 
 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)