clk: tegra: Use generic tegra_osc_clk_init() on Tegra114

There is no reason why Tegra114 cannot use the same generic code to set
up the oscillator, clk_m and pll_ref clocks. The only effective change
that this causes is that the CLK_SET_PARENT_RATE flag is dropped, but
since these clocks are all fixed it is not needed anyway.

Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 75d8af6213e74e9db8916da5f71c333274a39cd8..8237d16b407597dab129c5a277802190898a061f 100644 (file)
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -940,36 +940,6 @@ static struct clk **clks;
 static unsigned long osc_freq;
 static unsigned long pll_ref_freq;
 
-static int __init tegra114_osc_clk_init(void __iomem *clk_base)
-{
-       struct clk *clk;
-       u32 val, pll_ref_div;
-
-       val = readl_relaxed(clk_base + OSC_CTRL);
-
-       osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT];
-       if (!osc_freq) {
-               WARN_ON(1);
-               return -EINVAL;
-       }
-
-       /* clk_m */
-       clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
-                                     osc_freq);
-       clks[TEGRA114_CLK_CLK_M] = clk;
-
-       /* pll_ref */
-       val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
-       pll_ref_div = 1 << val;
-       clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
-                                       CLK_SET_RATE_PARENT, 1, pll_ref_div);
-       clks[TEGRA114_CLK_PLL_REF] = clk;
-
-       pll_ref_freq = osc_freq / pll_ref_div;
-
-       return 0;
-}
-
 static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
 {
        struct clk *clk;
@@ -1505,7 +1475,9 @@ static void __init tegra114_clock_init(struct device_node *np)
        if (!clks)
                return;
 
-       if (tegra114_osc_clk_init(clk_base) < 0)
+       if (tegra_osc_clk_init(clk_base, tegra114_clks, tegra114_input_freq,
+                              ARRAY_SIZE(tegra114_input_freq), 1, &osc_freq,
+                              &pll_ref_freq) < 0)
                return;
 
        tegra114_fixed_clk_init(clk_base);