OMAPDSS: DSI: Fix PLL_SELFEQDCO field width

PLL_SELFREQDCO bitfield is from bit 3 to 1, but the driver writes bits
from 4 to 1. The bit 4 is 'reserved', so this probably should not cause
any issues, but it's better to fix it.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

diff --git a/drivers/video/fbdev/omap2/dss/dsi.c b/drivers/video/fbdev/omap2/dss/dsi.c
index 947bd7b93375e4205b60ff5477da673bbca18619..0793bc67a275864ece56a4a8605553c5535704ea 100644 (file)
--- a/drivers/video/fbdev/omap2/dss/dsi.c
+++ b/drivers/video/fbdev/omap2/dss/dsi.c
@@ -1603,7 +1603,7 @@ int dsi_pll_set_clock_div(struct platform_device *dsidev,
        } else if (dss_has_feature(FEAT_DSI_PLL_SELFREQDCO)) {
                f = cinfo->clkin4ddr < 1000000000 ? 0x2 : 0x4;
 
-               l = FLD_MOD(l, f, 4, 1);        /* PLL_SELFREQDCO */
+               l = FLD_MOD(l, f, 3, 1);        /* PLL_SELFREQDCO */
        }
 
        l = FLD_MOD(l, 1, 13, 13);              /* DSI_PLL_REFEN */