ath9k: Fix eifs/usec timeout for AR9287 v1.3+
authorRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Sat, 27 Aug 2011 06:43:21 +0000 (12:13 +0530)
committerJohn W. Linville <linville@tuxdriver.com>
Mon, 29 Aug 2011 19:33:02 +0000 (15:33 -0400)
For AR9287 v1.3+ chips, MAC runs at 117MHz. But the initvals
IFS parameters are loaded based on 44/88MHz clockrate. So
eifs/usec from ini should not be used for AR9287 v1.3+.
The mentioned values are tested on 2 chain HT40 mode.

Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/hw.c
drivers/net/wireless/ath/ath9k/reg.h

index 4ba0ee91d43aa32bccdc6fe7edb60a27aa362c10..3a16ba256ef9456785692eb3607441c36222d199 100644 (file)
@@ -997,8 +997,14 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah)
                slottime = 21;
                sifstime = 64;
        } else {
-               eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/common->clockrate;
-               reg = REG_READ(ah, AR_USEC);
+               if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
+                       eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
+                       reg = AR_USEC_ASYNC_FIFO;
+               } else {
+                       eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
+                               common->clockrate;
+                       reg = REG_READ(ah, AR_USEC);
+               }
                rx_lat = MS(reg, AR_USEC_RX_LAT);
                tx_lat = MS(reg, AR_USEC_TX_LAT);
 
index a3b8bbc6c0635fd1a2f9a756af4940fc5669eb42..17a272f4d8d6aa230a85eb09af75164cf2ef9687 100644 (file)
 #define AR_D_GBL_IFS_EIFS         0x10b0
 #define AR_D_GBL_IFS_EIFS_M       0x0000FFFF
 #define AR_D_GBL_IFS_EIFS_RESV0   0xFFFF0000
+#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO 363
 
 #define AR_D_GBL_IFS_MISC        0x10f0
 #define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL        0x00000007
@@ -1503,6 +1504,7 @@ enum {
 #define AR_USEC_TX_LAT_S     14
 #define AR_USEC_RX_LAT       0x1F800000
 #define AR_USEC_RX_LAT_S     23
+#define AR_USEC_ASYNC_FIFO   0x12E00074
 
 #define AR_RESET_TSF        0x8020
 #define AR_RESET_TSF_ONCE   0x01000000