drm/i915/skl: Enable Per context Preemption granularity control

Per context preemption granularity control is only available from SKL:E0+

Actual WA is to disable percontext preemption granularity control until D0
which is the default case so this is equivalent to the inverse of
WaDisablePerCtxtPreemptionGranularityControl:skl

v2: add some detail to commit msg (Chris)

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Cc: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453412634-29238-8-git-send-email-arun.siluvery@linux.intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c51e7e909457217a7ada7c7dc39976ea472396ff..65e32a317d632bb246b813af3d3dcb9c4ce1ea6a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5995,6 +5995,9 @@ enum skl_disp_power_wells {
 #define SKL_DFSM_CDCLK_LIMIT_450       (2 << 23)
 #define SKL_DFSM_CDCLK_LIMIT_337_5     (3 << 23)
 
+#define GEN7_FF_SLICE_CS_CHICKEN1      _MMIO(0x20e0)
+#define   GEN9_FFSC_PERCTX_PREEMPT_CTRL        (1<<14)
+
 #define FF_SLICE_CS_CHICKEN2                   _MMIO(0x20e4)
 #define  GEN9_TSG_BARRIER_ACK_DISABLE          (1<<8)
 

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 262a7ea9e9c40d3c1c7283ed7c43a522249bcddd..d07c6a9e7b40c1127be00baa15daa4167119e7f3 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1046,6 +1046,16 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
        if (ret)
                return ret;
 
+       /*
+        * Actual WA is to disable percontext preemption granularity control
+        * until D0 which is the default case so this is equivalent to
+        * !WaDisablePerCtxtPreemptionGranularityControl:skl
+        */
+       if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
+               I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
+                          _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
+       }
+
        if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
                /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
                I915_WRITE(FF_SLICE_CS_CHICKEN2,