This patch adds the CPU clocks so that the CPU DVFS can be enabled.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Jon Medhurst (Tixy) <tixy@linaro.org>
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A57_L2>;
+ clocks = <&scpi_dvfs 0>;
};
A57_1: cpu@1 {
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A57_L2>;
+ clocks = <&scpi_dvfs 0>;
};
A53_0: cpu@100 {
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ clocks = <&scpi_dvfs 1>;
};
A53_1: cpu@101 {
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ clocks = <&scpi_dvfs 1>;
};
A53_2: cpu@102 {
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ clocks = <&scpi_dvfs 1>;
};
A53_3: cpu@103 {
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ clocks = <&scpi_dvfs 1>;
};
A57_L2: l2-cache0 {
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A57_L2>;
+ clocks = <&scpi_dvfs 0>;
};
A57_1: cpu@1 {
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A57_L2>;
+ clocks = <&scpi_dvfs 0>;
};
A53_0: cpu@100 {
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ clocks = <&scpi_dvfs 1>;
};
A53_1: cpu@101 {
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ clocks = <&scpi_dvfs 1>;
};
A53_2: cpu@102 {
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ clocks = <&scpi_dvfs 1>;
};
A53_3: cpu@103 {
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ clocks = <&scpi_dvfs 1>;
};
A57_L2: l2-cache0 {