ARM: shmobile: r8a7790: Add Audio CTU support on DTSI
authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tue, 21 Jul 2015 00:26:20 +0000 (00:26 +0000)
committerSimon Horman <horms+renesas@verge.net.au>
Wed, 22 Jul 2015 00:36:10 +0000 (09:36 +0900)
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/r8a7790.dtsi
include/dt-bindings/clock/r8a7790-clock.h

index 3ae0c3bfb9b9613056bdb0f1a01a4f31f8bc625e..6aa1d759690b2403cb43a467439dc36a4e7ef97c 100644 (file)
                                <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
                                <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
                                <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
+                               <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
                                <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
 
                        #clock-cells = <1>;
                                R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
                                R8A7790_CLK_SCU_ALL
                                R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
+                               R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0
                                R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
                                R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
                        >;
                                "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
                                "scu-all",
                                "scu-dvc1", "scu-dvc0",
+                               "scu-ctu1-mix1", "scu-ctu0-mix0",
                                "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
                                "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
                };
                        <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
                        <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
                        <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
+                       <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
                        <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
                        <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
                clock-names = "ssi-all",
                                "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
                                "src.9", "src.8", "src.7", "src.6", "src.5",
                                "src.4", "src.3", "src.2", "src.1", "src.0",
+                               "ctu.0", "ctu.1",
                                "dvc.0", "dvc.1",
                                "clk_a", "clk_b", "clk_c", "clk_i";
 
                        };
                };
 
+               rcar_sound,ctu {
+                       ctu00: ctu@0 { };
+                       ctu01: ctu@1 { };
+                       ctu02: ctu@2 { };
+                       ctu03: ctu@3 { };
+                       ctu10: ctu@4 { };
+                       ctu11: ctu@5 { };
+                       ctu12: ctu@6 { };
+                       ctu13: ctu@7 { };
+               };
+
                rcar_sound,src {
                        src0: src@0 {
                                interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
index e119ef372ba39754641ac5719b3487a2ba980d20..7b1ad8922eecdc50afd5bdeb4bb951c0f0c75e81 100644 (file)
 #define R8A7790_CLK_SCU_ALL            17
 #define R8A7790_CLK_SCU_DVC1           18
 #define R8A7790_CLK_SCU_DVC0           19
+#define R8A7790_CLK_SCU_CTU1_MIX1      20
+#define R8A7790_CLK_SCU_CTU0_MIX0      21
 #define R8A7790_CLK_SCU_SRC9           22
 #define R8A7790_CLK_SCU_SRC8           23
 #define R8A7790_CLK_SCU_SRC7           24