drm/i915: Configure GAM_ECOCHK appropriatly for Gen7

IVB and HSW use different encodings for the PPGTT cacheability bits in
the GAM_ECOCHK register.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index fae638072d7d1bba9f6201110597d60257324d72..b77e98c0812c8674fc974b3a97c27cb9221fec10 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -117,12 +117,19 @@ static int gen6_ppgtt_enable(struct drm_device *dev)
                                       ECOCHK_PPGTT_CACHE64B);
                I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
        } else if (INTEL_INFO(dev)->gen >= 7) {
-               uint32_t ecobits;
+               uint32_t ecochk, ecobits;
 
                ecobits = I915_READ(GAC_ECO_BITS);
                I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 
-               I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
+               ecochk = I915_READ(GAM_ECOCHK);
+               if (IS_HASWELL(dev)) {
+                       ecochk |= ECOCHK_PPGTT_WB_HSW;
+               } else {
+                       ecochk |= ECOCHK_PPGTT_LLC_IVB;
+                       ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
+               }
+               I915_WRITE(GAM_ECOCHK, ecochk);
                /* GFX_MODE is per-ring on gen7+ */
        }
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 96b361f9a32dcd1c49d4523ce1a47ad82adf915a..3b9ec9bcd383dd7950eda614556cbd16f4d934e6 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -125,6 +125,11 @@
 #define   HSW_ECOCHK_ARB_PRIO_SOL      (1<<6)
 #define   ECOCHK_PPGTT_CACHE64B                (0x3<<3)
 #define   ECOCHK_PPGTT_CACHE4B         (0x0<<3)
+#define   ECOCHK_PPGTT_GFDT_IVB                (0x1<<4)
+#define   ECOCHK_PPGTT_LLC_IVB         (0x1<<3)
+#define   ECOCHK_PPGTT_UC_HSW          (0x1<<3)
+#define   ECOCHK_PPGTT_WT_HSW          (0x2<<3)
+#define   ECOCHK_PPGTT_WB_HSW          (0x3<<3)
 
 #define GAC_ECO_BITS                   0x14090
 #define   ECOBITS_SNB_BIT              (1<<13)