ath9k: Fix baseband watchdog interrupts
authorSujith Manoharan <c_manoha@qca.qualcomm.com>
Tue, 24 Dec 2013 05:14:22 +0000 (10:44 +0530)
committerJohn W. Linville <linville@tuxdriver.com>
Fri, 3 Jan 2014 20:36:57 +0000 (15:36 -0500)
Program the required baseband watchdog interrupt
mask to ensure that the correct watchdog interrupts
are raised when the BB is hung for some reason.

Also, use the capability HW_BB_WATCHDOG instead of
relying on other flags.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/mac.c
drivers/net/wireless/ath/ath9k/main.c
drivers/net/wireless/ath/ath9k/reg.h

index 89d7e206992b2ec28fb100b109d7b9e63d4a441d..5f727588ca2788b0e598ccf98450af8f396c7135 100644 (file)
@@ -922,11 +922,29 @@ void ath9k_hw_set_interrupts(struct ath_hw *ah)
                        mask2 |= AR_IMR_S2_CST;
        }
 
+       if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) {
+               if (ints & ATH9K_INT_BB_WATCHDOG) {
+                       mask |= AR_IMR_BCNMISC;
+                       mask2 |= AR_IMR_S2_BB_WATCHDOG;
+               }
+       }
+
        ath_dbg(common, INTERRUPT, "new IMR 0x%x\n", mask);
        REG_WRITE(ah, AR_IMR, mask);
-       ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
-                          AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
-                          AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
+       ah->imrs2_reg &= ~(AR_IMR_S2_TIM |
+                          AR_IMR_S2_DTIM |
+                          AR_IMR_S2_DTIMSYNC |
+                          AR_IMR_S2_CABEND |
+                          AR_IMR_S2_CABTO |
+                          AR_IMR_S2_TSFOOR |
+                          AR_IMR_S2_GTT |
+                          AR_IMR_S2_CST);
+
+       if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) {
+               if (ints & ATH9K_INT_BB_WATCHDOG)
+                       ah->imrs2_reg &= ~AR_IMR_S2_BB_WATCHDOG;
+       }
+
        ah->imrs2_reg |= mask2;
        REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
 
index ba00a319481663a1beba07db38a8853a173141f8..1fd69de79020aef652cd639269ff15c5265c74d6 100644 (file)
@@ -587,7 +587,7 @@ irqreturn_t ath_isr(int irq, void *dev)
            !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
                goto chip_reset;
 
-       if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
+       if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
            (status & ATH9K_INT_BB_WATCHDOG)) {
 
                spin_lock(&common->cc_lock);
@@ -726,11 +726,13 @@ static int ath9k_start(struct ieee80211_hw *hw)
 
        if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
                ah->imask |= ATH9K_INT_RXHP |
-                            ATH9K_INT_RXLP |
-                            ATH9K_INT_BB_WATCHDOG;
+                            ATH9K_INT_RXLP;
        else
                ah->imask |= ATH9K_INT_RX;
 
+       if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
+               ah->imask |= ATH9K_INT_BB_WATCHDOG;
+
        ah->imask |= ATH9K_INT_GTT;
 
        if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
index 9ad007312c9d4fa53b5c9365c3950f3fbfbb7a86..c9a8b777749154af2f35e790aaa2c97cb53bc311 100644 (file)
 #define AR_IMR_S2              0x00ac
 #define AR_IMR_S2_QCU_TXURN    0x000003FF
 #define AR_IMR_S2_QCU_TXURN_S  0
+#define AR_IMR_S2_BB_WATCHDOG  0x00010000
 #define AR_IMR_S2_CST          0x00400000
 #define AR_IMR_S2_GTT          0x00800000
 #define AR_IMR_S2_TIM          0x01000000