arm64: dts: r8a7796: Add CA53 L2 cache-controller node

Add a device node for the Cortex-A53 L2 cache-controller.

The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).

Extracted from a patch by Takeshi Kihara in the BSP.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 454e1292f9108b34a996469fd7bac8f81f0b79d7..b951f5ffe9e0faa0d75853c23146e7966f0a4b0c 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -61,6 +61,13 @@
                        cache-unified;
                        cache-level = <2>;
                };
+
+               L2_CA53: cache-controller-1 {
+                       compatible = "cache";
+                       power-domains = <&sysc R8A7796_PD_CA53_SCU>;
+                       cache-unified;
+                       cache-level = <2>;
+               };
        };
 
        extal_clk: extal {