EEPROM_SIZE / sizeof(u16));
}
+static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
+{
+ u32 reg;
+
+ rt2800_register_read(rt2x00dev, EFUSE_CTRL, ®);
+
+ return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
+}
+
static void rt2800pci_efuse_read(struct rt2x00_dev *rt2x00dev,
unsigned int i)
{
{
}
+static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
+{
+ return 0;
+}
+
static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
{
}
case RT3052:
rt2800pci_read_eeprom_soc(rt2x00dev);
break;
- case RT3090:
- rt2800pci_read_eeprom_efuse(rt2x00dev);
- break;
default:
- rt2800pci_read_eeprom_pci(rt2x00dev);
+ if (rt2800pci_efuse_detect(rt2x00dev))
+ rt2800pci_read_eeprom_efuse(rt2x00dev);
+ else
+ rt2800pci_read_eeprom_pci(rt2x00dev);
break;
}
#define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
#define EFUSE_CTRL_MODE FIELD32(0x000000c0)
#define EFUSE_CTRL_KICK FIELD32(0x40000000)
+#define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
/*
* EFUSE_DATA0