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drm/i915: Add TIMESTAMP to register whitelist
authorJordan Justen <jordan.l.justen@intel.com>
Mon, 7 Mar 2016 07:30:26 +0000 (23:30 -0800)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 21 Mar 2016 08:56:42 +0000 (09:56 +0100)
This is needed for the Mesa Vulkan driver on Haswell.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1457335830-30923-2-git-send-email-jordan.l.justen@intel.com
drivers/gpu/drm/i915/i915_cmd_parser.c patch | blob | blame | history

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 2c50142be55973e70ca7bb3cd52e7b5b9c7fa5d6..a5ebe9a13a11bb5b9fda912c1eee2a114ea7c825 100644 (file)
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -444,6 +444,7 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
        REG64(CL_PRIMITIVES_COUNT),
        REG64(PS_INVOCATION_COUNT),
        REG64(PS_DEPTH_COUNT),
+       REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
        REG32(OACONTROL), /* Only allowed for LRI and SRM. See below. */
        REG64(MI_PREDICATE_SRC0),
        REG64(MI_PREDICATE_SRC1),