bcm47xx: make it possible to build bcm47xx without ssb.
authorHauke Mehrtens <hauke@hauke-m.de>
Fri, 22 Jul 2011 23:20:13 +0000 (01:20 +0200)
committerJohn W. Linville <linville@tuxdriver.com>
Mon, 8 Aug 2011 18:29:31 +0000 (14:29 -0400)
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
12 files changed:
arch/mips/Kconfig
arch/mips/bcm47xx/Kconfig [new file with mode: 0644]
arch/mips/bcm47xx/Makefile
arch/mips/bcm47xx/gpio.c
arch/mips/bcm47xx/nvram.c
arch/mips/bcm47xx/serial.c
arch/mips/bcm47xx/setup.c
arch/mips/bcm47xx/time.c
arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
arch/mips/include/asm/mach-bcm47xx/gpio.h
arch/mips/pci/pci-bcm47xx.c
drivers/watchdog/bcm47xx_wdt.c

index 177cdaf835644fdf613dbafd203a8e2dcf0e08d3..0dbb4edc2dd18e1322cd7f164d8d272d06cf3746 100644 (file)
@@ -91,15 +91,8 @@ config BCM47XX
        select DMA_NONCOHERENT
        select HW_HAS_PCI
        select IRQ_CPU
-       select SYS_HAS_CPU_MIPS32_R1
        select SYS_SUPPORTS_32BIT_KERNEL
        select SYS_SUPPORTS_LITTLE_ENDIAN
-       select SSB
-       select SSB_DRIVER_MIPS
-       select SSB_DRIVER_EXTIF
-       select SSB_EMBEDDED
-       select SSB_B43_PCI_BRIDGE if PCI
-       select SSB_PCICORE_HOSTMODE if PCI
        select GENERIC_GPIO
        select SYS_HAS_EARLY_PRINTK
        select CFE
@@ -788,6 +781,7 @@ endchoice
 
 source "arch/mips/alchemy/Kconfig"
 source "arch/mips/ath79/Kconfig"
+source "arch/mips/bcm47xx/Kconfig"
 source "arch/mips/bcm63xx/Kconfig"
 source "arch/mips/jazz/Kconfig"
 source "arch/mips/jz4740/Kconfig"
diff --git a/arch/mips/bcm47xx/Kconfig b/arch/mips/bcm47xx/Kconfig
new file mode 100644 (file)
index 0000000..0346f92
--- /dev/null
@@ -0,0 +1,18 @@
+if BCM47XX
+
+config BCM47XX_SSB
+       bool "SSB Support for Broadcom BCM47XX"
+       select SYS_HAS_CPU_MIPS32_R1
+       select SSB
+       select SSB_DRIVER_MIPS
+       select SSB_DRIVER_EXTIF
+       select SSB_EMBEDDED
+       select SSB_B43_PCI_BRIDGE if PCI
+       select SSB_PCICORE_HOSTMODE if PCI
+       default y
+       help
+        Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support.
+
+        This will generate an image with support for SSB and MIPS32 R1 instruction set.
+
+endif
index 7465e8a72d9a674cd425bb705e99bbd6eb2cfff4..4add17349ff9549a264da1814249ae533144e042 100644 (file)
@@ -3,4 +3,5 @@
 # under Linux.
 #
 
-obj-y := gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o
+obj-y                          += gpio.o irq.o nvram.o prom.o serial.o setup.o time.o
+obj-$(CONFIG_BCM47XX_SSB)      += wgt634u.o
index 99e1c50caf6b6ae40bc9c81f226775211c20646f..2b804c36750bb5c7051e2fcc02ae045935490ba4 100644 (file)
@@ -21,6 +21,7 @@ static DECLARE_BITMAP(gpio_in_use, BCM47XX_EXTIF_GPIO_LINES);
 int gpio_request(unsigned gpio, const char *tag)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) &&
                    ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES))
@@ -34,6 +35,7 @@ int gpio_request(unsigned gpio, const char *tag)
                        return -EBUSY;
 
                return 0;
+#endif
        }
        return -EINVAL;
 }
@@ -42,6 +44,7 @@ EXPORT_SYMBOL(gpio_request);
 void gpio_free(unsigned gpio)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) &&
                    ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES))
@@ -53,6 +56,7 @@ void gpio_free(unsigned gpio)
 
                clear_bit(gpio, gpio_in_use);
                return;
+#endif
        }
 }
 EXPORT_SYMBOL(gpio_free);
@@ -60,6 +64,7 @@ EXPORT_SYMBOL(gpio_free);
 int gpio_to_irq(unsigned gpio)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco))
                        return ssb_mips_irq(bcm47xx_bus.ssb.chipco.dev) + 2;
@@ -67,6 +72,7 @@ int gpio_to_irq(unsigned gpio)
                        return ssb_mips_irq(bcm47xx_bus.ssb.extif.dev) + 2;
                else
                        return -EINVAL;
+#endif
        }
        return -EINVAL;
 }
index bcac2ffd1248950a5dbcd461fe7bfcddb9ad36e8..4e994edb142501a89821fdc5ea28144d30ea3722 100644 (file)
@@ -26,7 +26,9 @@ static char nvram_buf[NVRAM_SPACE];
 /* Probe for NVRAM header */
 static void early_nvram_init(void)
 {
+#ifdef CONFIG_BCM47XX_SSB
        struct ssb_mipscore *mcore_ssb;
+#endif
        struct nvram_header *header;
        int i;
        u32 base = 0;
@@ -35,11 +37,13 @@ static void early_nvram_init(void)
        u32 *src, *dst;
 
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                mcore_ssb = &bcm47xx_bus.ssb.mipscore;
                base = mcore_ssb->flash_window;
                lim = mcore_ssb->flash_window_size;
                break;
+#endif
        }
 
        off = FLASH_MIN;
index 17c67e24b5498e0534ff98df70fd6839527806e4..fcef68836979753b7900f46ae5de6bd96d9f03c3 100644 (file)
@@ -23,6 +23,7 @@ static struct platform_device uart8250_device = {
        },
 };
 
+#ifdef CONFIG_BCM47XX_SSB
 static int __init uart8250_init_ssb(void)
 {
        int i;
@@ -44,12 +45,15 @@ static int __init uart8250_init_ssb(void)
        }
        return platform_device_register(&uart8250_device);
 }
+#endif
 
 static int __init uart8250_init(void)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                return uart8250_init_ssb();
+#endif
        }
        return -EINVAL;
 }
index 271cedb339ae0abb0807d554f66ce6e188a0900d..142cf1bc8884f8657d0c24052d2127364a9aa6b9 100644 (file)
@@ -47,9 +47,11 @@ static void bcm47xx_machine_restart(char *command)
        local_irq_disable();
        /* Set the watchdog timer to reset immediately */
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 1);
                break;
+#endif
        }
        while (1)
                cpu_relax();
@@ -60,14 +62,17 @@ static void bcm47xx_machine_halt(void)
        /* Disable interrupts and watchdog and spin forever */
        local_irq_disable();
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0);
                break;
+#endif
        }
        while (1)
                cpu_relax();
 }
 
+#ifdef CONFIG_BCM47XX_SSB
 #define READ_FROM_NVRAM(_outvar, name, buf) \
        if (nvram_getprefix(prefix, name, buf, sizeof(buf)) >= 0)\
                sprom->_outvar = simple_strtoul(buf, NULL, 0);
@@ -288,13 +293,16 @@ static void __init bcm47xx_register_ssb(void)
                }
        }
 }
+#endif
 
 void __init plat_mem_setup(void)
 {
        struct cpuinfo_mips *c = &current_cpu_data;
 
+#ifdef CONFIG_BCM47XX_SSB
        bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB;
        bcm47xx_register_ssb();
+#endif
 
        _machine_restart = bcm47xx_machine_restart;
        _machine_halt = bcm47xx_machine_halt;
index 50aea2e1808c5fb0f06dcbc6ee474f21f5d75c80..03dfc65b1b60f4c3d02558d31f3834d7c9f18a5b 100644 (file)
@@ -40,9 +40,11 @@ void __init plat_time_init(void)
        write_c0_compare(0xffff);
 
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2;
                break;
+#endif
        }
 
        if (!hz)
index 7cf481bb1a05ada49b3466cda9cb96f6ea0c7b23..d037afb6677e186daba8580b68b76812bedbc0a6 100644 (file)
 #include <linux/ssb/ssb.h>
 
 enum bcm47xx_bus_type {
+#ifdef CONFIG_BCM47XX_SSB
        BCM47XX_BUS_TYPE_SSB,
+#endif
 };
 
 union bcm47xx_bus {
+#ifdef CONFIG_BCM47XX_SSB
        struct ssb_bus ssb;
+#endif
 };
 
 extern union bcm47xx_bus bcm47xx_bus;
index 6b78827dd140e17174041e93e2f6fe540d1e23b2..1d5f5af56b5fd8e54247e7d0007bf60927f6fd60 100644 (file)
@@ -22,8 +22,10 @@ extern int gpio_to_irq(unsigned gpio);
 static inline int gpio_get_value(unsigned gpio)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                return ssb_gpio_in(&bcm47xx_bus.ssb, 1 << gpio);
+#endif
        }
        return -EINVAL;
 }
@@ -31,18 +33,22 @@ static inline int gpio_get_value(unsigned gpio)
 static inline void gpio_set_value(unsigned gpio, int value)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio,
                             value ? 1 << gpio : 0);
+#endif
        }
 }
 
 static inline int gpio_direction_input(unsigned gpio)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 0);
                return 0;
+#endif
        }
        return -EINVAL;
 }
@@ -50,6 +56,7 @@ static inline int gpio_direction_input(unsigned gpio)
 static inline int gpio_direction_output(unsigned gpio, int value)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                /* first set the gpio out value */
                ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio,
@@ -57,6 +64,7 @@ static inline int gpio_direction_output(unsigned gpio, int value)
                /* then set the gpio mode */
                ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 1 << gpio);
                return 0;
+#endif
        }
        return -EINVAL;
 }
@@ -64,10 +72,12 @@ static inline int gpio_direction_output(unsigned gpio, int value)
 static inline int gpio_intmask(unsigned gpio, int value)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                ssb_gpio_intmask(&bcm47xx_bus.ssb, 1 << gpio,
                                 value ? 1 << gpio : 0);
                return 0;
+#endif
        }
        return -EINVAL;
 }
@@ -75,10 +85,12 @@ static inline int gpio_intmask(unsigned gpio, int value)
 static inline int gpio_polarity(unsigned gpio, int value)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                ssb_gpio_polarity(&bcm47xx_bus.ssb, 1 << gpio,
                                  value ? 1 << gpio : 0);
                return 0;
+#endif
        }
        return -EINVAL;
 }
index 455f8e50a0070b6be32c0e2c0cde56af487aafac..400535a955d02daea0b4c96a836b5f2ac6cc8854 100644 (file)
@@ -25,6 +25,7 @@
 #include <linux/types.h>
 #include <linux/pci.h>
 #include <linux/ssb/ssb.h>
+#include <bcm47xx.h>
 
 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
@@ -33,9 +34,13 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 
 int pcibios_plat_dev_init(struct pci_dev *dev)
 {
+#ifdef CONFIG_BCM47XX_SSB
        int res;
        u8 slot, pin;
 
+       if (bcm47xx_bus_type !=  BCM47XX_BUS_TYPE_SSB)
+               return 0;
+
        res = ssb_pcibios_plat_dev_init(dev);
        if (res < 0) {
                printk(KERN_ALERT "PCI: Failed to init device %s\n",
@@ -55,5 +60,6 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
        }
 
        dev->irq = res;
+#endif
        return 0;
 }
index c43406c48613c85865a29681ba03e6bea648667c..6b037024464f9e0cf156122e571eedd69a564fa1 100644 (file)
@@ -55,17 +55,21 @@ static inline void bcm47xx_wdt_hw_start(void)
 {
        /* this is 2,5s on 100Mhz clock  and 2s on 133 Mhz */
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0xfffffff);
                break;
+#endif
        }
 }
 
 static inline int bcm47xx_wdt_hw_stop(void)
 {
        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
        case BCM47XX_BUS_TYPE_SSB:
                return ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0);
+#endif
        }
        return -EINVAL;
 }