projects
/
GitHub
/
LineageOS
/
android_kernel_motorola_exynos9610.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
f6fc73f
)
powerpc/oops: Line up NIP & MSR with other rows
author
Michael Ellerman
<mpe@ellerman.id.au>
Wed, 23 Aug 2017 13:56:24 +0000
(23:56 +1000)
committer
Michael Ellerman
<mpe@ellerman.id.au>
Mon, 28 Aug 2017 12:10:00 +0000
(22:10 +1000)
This is purely cosmetic, but does look nicer IMHO:
Before:
task:
c000000001453400
task.stack:
c000000001c6c000
NIP:
c000000000a0fbfc
LR:
c000000000a0fbf4
CTR:
c000000000ba6220
REGS:
c0000001fffef820
TRAP: 0300 Not tainted (
4.13.0-rc6-gcc-6.3.1-00234-g423af27f7d81
)
MSR:
8000000000009033
<SF,EE,ME,IR,DR,RI,LE> CR:
88088242
XER:
00000000
CFAR:
c0000000000b3488
DAR:
0000000000000000
DSISR:
42000000
SOFTE: 0
After:
task:
c000000001453400
task.stack:
c000000001c6c000
NIP:
c000000000a0fbfc
LR:
c000000000a0fbf4
CTR:
c000000000ba6220
REGS:
c0000001fffef820
TRAP: 0300 Not tainted (
4.13.0-rc6-gcc-6.3.1-00234-g423af27f7d81
-dirty)
MSR:
8000000000009033
<SF,EE,ME,IR,DR,RI,LE> CR:
88088242
XER:
00000000
CFAR:
c0000000000b34a4
DAR:
0000000000000000
DSISR:
42000000
SOFTE: 0
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
arch/powerpc/kernel/process.c
patch
|
blob
|
blame
|
history
diff --git
a/arch/powerpc/kernel/process.c
b/arch/powerpc/kernel/process.c
index 1e24d6f1be90dda2059e470fa0c49c18721b9347..a0c74bbf345426bc9918860a203b8ab3427a3390 100644
(file)
--- a/
arch/powerpc/kernel/process.c
+++ b/
arch/powerpc/kernel/process.c
@@
-1380,11
+1380,11
@@
void show_regs(struct pt_regs * regs)
show_regs_print_info(KERN_DEFAULT);
- printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
+ printk("NIP:
"REG" LR: "REG" CTR: "REG"\n",
regs->nip, regs->link, regs->ctr);
printk("REGS: %p TRAP: %04lx %s (%s)\n",
regs, regs->trap, print_tainted(), init_utsname()->release);
- printk("MSR: "REG" ", regs->msr);
+ printk("MSR:
"REG" ", regs->msr);
print_msr_bits(regs->msr);
pr_cont(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
trap = TRAP(regs);