Merge tag 'v3.3-rc2' into depends/rmk/for-armsoc

There were conflicts between fixes going in after 3.3-rc1 and
Russell's stable arm-soc base branch. Resolving it in the dependency
branch so that each topic branch shares the same resolution.

Conflicts:
	arch/arm/mach-at91/at91cap9.c
	arch/arm/mach-at91/at91sam9g45.c

diff --cc arch/arm/mach-at91/at91cap9.c
index 1d29a6cbbae28fcc8fa32b20516ee6821ecae6af,a42edc25a87e693aea85b2b494515c14e4d32c42..8967d75c2ea3d4c4570efa8c77709b97d623eada
--- 1/arch/arm/mach-at91/at91cap9.c
--- 2/arch/arm/mach-at91/at91cap9.c
+++ b/arch/arm/mach-at91/at91cap9.c
@@@ -315,17 -313,6 +314,12 @@@ static struct at91_gpio_bank at91cap9_g
        }
  };
  
- static void at91cap9_restart(char mode, const char *cmd)
- {
-       at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
- }
- 
 +static void at91cap9_idle(void)
 +{
 +      at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
 +      cpu_do_idle();
 +}
 +
  /* --------------------------------------------------------------------
   *  AT91CAP9 processor initialization
   * -------------------------------------------------------------------- */
@@@ -344,8 -332,7 +339,8 @@@ static void __init at91cap9_ioremap_reg
  
  static void __init at91cap9_initialize(void)
  {
-       arm_pm_restart = at91cap9_restart;
 +      arm_pm_idle = at91cap9_idle;
+       arm_pm_restart = at91sam9g45_restart;
        at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
  
        /* Register GPIO subsystem */

diff --cc arch/arm/mach-at91/at91sam9260.c
Simple merge

diff --cc arch/arm/mach-at91/at91sam9261.c
Simple merge

diff --cc arch/arm/mach-at91/at91sam9263.c
Simple merge

diff --cc arch/arm/mach-at91/at91sam9g45.c
index 0e80b395214d9a256fb624304ea95e3c94c000f1,1cb6a96b1c1e3a7ec44cbde4129992b1f54da5eb..5b12192e52ecc59e8fde425146f8811469149179
--- 1/arch/arm/mach-at91/at91sam9g45.c
--- 2/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@@ -318,17 -317,6 +317,12 @@@ static struct at91_gpio_bank at91sam9g4
        }
  };
  
- static void at91sam9g45_restart(char mode, const char *cmd)
- {
-       at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
- }
- 
 +static void at91sam9g45_idle(void)
 +{
 +      at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
 +      cpu_do_idle();
 +}
 +
  /* --------------------------------------------------------------------
   *  AT91SAM9G45 processor initialization
   * -------------------------------------------------------------------- */

diff --cc arch/arm/mach-at91/at91sam9rl.c
Simple merge

diff --cc arch/arm/mach-imx/mm-imx5.c
index 0000000000000000000000000000000000000000,bc17dfea38170872c24216165715e8af60144feb..49549a72dc7dbb2de0c8d1e75af06deddbef2a59
mode 000000,100644..100644
--- /dev/null
--- 2/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@@ -1,0 -1,209 +1,203 @@@
 -      if (!need_resched()) {
 -              /* gpc clock is needed for SRPG */
 -              if (gpc_dvfs_clk == NULL) {
 -                      gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
 -                      if (IS_ERR(gpc_dvfs_clk))
 -                              goto err0;
 -              }
 -              clk_enable(gpc_dvfs_clk);
 -              mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
 -              if (tzic_enable_wake())
 -                      goto err1;
 -              cpu_do_idle();
 -err1:
 -              clk_disable(gpc_dvfs_clk);
+ /*
+  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+  *
+  * The code contained herein is licensed under the GNU General Public
+  * License.  You may obtain a copy of the GNU General Public License
+  * Version 2 or later at the following locations:
+  *
+  * http://www.opensource.org/licenses/gpl-license.html
+  * http://www.gnu.org/copyleft/gpl.html
+  *
+  * Create static mapping between physical to virtual memory.
+  */
+ 
+ #include <linux/mm.h>
+ #include <linux/init.h>
+ #include <linux/clk.h>
+ 
+ #include <asm/mach/map.h>
+ 
+ #include <mach/hardware.h>
+ #include <mach/common.h>
+ #include <mach/devices-common.h>
+ #include <mach/iomux-v3.h>
+ 
+ static struct clk *gpc_dvfs_clk;
+ 
+ static void imx5_idle(void)
+ {
 -err0:
 -      local_irq_enable();
++      /* gpc clock is needed for SRPG */
++      if (gpc_dvfs_clk == NULL) {
++              gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
++              if (IS_ERR(gpc_dvfs_clk))
++                      return;
+       }
 -      pm_idle = imx5_idle;
++      clk_enable(gpc_dvfs_clk);
++      mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
++      if (tzic_enable_wake() != 0)
++              cpu_do_idle();
++      clk_disable(gpc_dvfs_clk);
+ }
+ 
+ /*
+  * Define the MX50 memory map.
+  */
+ static struct map_desc mx50_io_desc[] __initdata = {
+       imx_map_entry(MX50, TZIC, MT_DEVICE),
+       imx_map_entry(MX50, SPBA0, MT_DEVICE),
+       imx_map_entry(MX50, AIPS1, MT_DEVICE),
+       imx_map_entry(MX50, AIPS2, MT_DEVICE),
+ };
+ 
+ /*
+  * Define the MX51 memory map.
+  */
+ static struct map_desc mx51_io_desc[] __initdata = {
+       imx_map_entry(MX51, TZIC, MT_DEVICE),
+       imx_map_entry(MX51, IRAM, MT_DEVICE),
+       imx_map_entry(MX51, AIPS1, MT_DEVICE),
+       imx_map_entry(MX51, SPBA0, MT_DEVICE),
+       imx_map_entry(MX51, AIPS2, MT_DEVICE),
+ };
+ 
+ /*
+  * Define the MX53 memory map.
+  */
+ static struct map_desc mx53_io_desc[] __initdata = {
+       imx_map_entry(MX53, TZIC, MT_DEVICE),
+       imx_map_entry(MX53, AIPS1, MT_DEVICE),
+       imx_map_entry(MX53, SPBA0, MT_DEVICE),
+       imx_map_entry(MX53, AIPS2, MT_DEVICE),
+ };
+ 
+ /*
+  * This function initializes the memory map. It is called during the
+  * system startup to create static physical to virtual memory mappings
+  * for the IO modules.
+  */
+ void __init mx50_map_io(void)
+ {
+       iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
+ }
+ 
+ void __init mx51_map_io(void)
+ {
+       iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
+ }
+ 
+ void __init mx53_map_io(void)
+ {
+       iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
+ }
+ 
+ void __init imx50_init_early(void)
+ {
+       mxc_set_cpu_type(MXC_CPU_MX50);
+       mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
+       mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
+ }
+ 
+ void __init imx51_init_early(void)
+ {
+       mxc_set_cpu_type(MXC_CPU_MX51);
+       mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
+       mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
++      arm_pm_idle = imx5_idle;
+ }
+ 
+ void __init imx53_init_early(void)
+ {
+       mxc_set_cpu_type(MXC_CPU_MX53);
+       mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
+       mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
+ }
+ 
+ void __init mx50_init_irq(void)
+ {
+       tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
+ }
+ 
+ void __init mx51_init_irq(void)
+ {
+       tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
+ }
+ 
+ void __init mx53_init_irq(void)
+ {
+       tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
+ }
+ 
+ static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
+       .ap_2_ap_addr = 642,
+       .uart_2_mcu_addr = 817,
+       .mcu_2_app_addr = 747,
+       .mcu_2_shp_addr = 961,
+       .ata_2_mcu_addr = 1473,
+       .mcu_2_ata_addr = 1392,
+       .app_2_per_addr = 1033,
+       .app_2_mcu_addr = 683,
+       .shp_2_per_addr = 1251,
+       .shp_2_mcu_addr = 892,
+ };
+ 
+ static struct sdma_platform_data imx51_sdma_pdata __initdata = {
+       .fw_name = "sdma-imx51.bin",
+       .script_addrs = &imx51_sdma_script,
+ };
+ 
+ static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
+       .ap_2_ap_addr = 642,
+       .app_2_mcu_addr = 683,
+       .mcu_2_app_addr = 747,
+       .uart_2_mcu_addr = 817,
+       .shp_2_mcu_addr = 891,
+       .mcu_2_shp_addr = 960,
+       .uartsh_2_mcu_addr = 1032,
+       .spdif_2_mcu_addr = 1100,
+       .mcu_2_spdif_addr = 1134,
+       .firi_2_mcu_addr = 1193,
+       .mcu_2_firi_addr = 1290,
+ };
+ 
+ static struct sdma_platform_data imx53_sdma_pdata __initdata = {
+       .fw_name = "sdma-imx53.bin",
+       .script_addrs = &imx53_sdma_script,
+ };
+ 
+ void __init imx50_soc_init(void)
+ {
+       /* i.mx50 has the i.mx31 type gpio */
+       mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
+       mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
+       mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
+       mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
+       mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
+       mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
+ }
+ 
+ void __init imx51_soc_init(void)
+ {
+       /* i.mx51 has the i.mx31 type gpio */
+       mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
+       mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
+       mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
+       mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
+ 
+       /* i.mx51 has the i.mx35 type sdma */
+       imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
+ }
+ 
+ void __init imx53_soc_init(void)
+ {
+       /* i.mx53 has the i.mx31 type gpio */
+       mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
+       mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
+       mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
+       mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
+       mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
+       mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
+       mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
+ 
+       /* i.mx53 has the i.mx35 type sdma */
+       imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
+ }

diff --cc arch/arm/mach-realview/realview_eb.c
Simple merge

diff --cc arch/arm/mach-realview/realview_pb11mp.c
Simple merge

diff --cc arch/arm/mach-vexpress/ct-ca9x4.c
Simple merge