* Logical Physical
* e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
* ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
- * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
* fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
* ef000000 Cache flush
* f1000000 10000000 Core module registers
.pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
.length = SZ_16M,
.type = MT_DEVICE
- }, {
- .virtual = (unsigned long)PCI_V3_VADDR,
- .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE),
- .length = SZ_64K,
- .type = MT_DEVICE
}
};
* the mappings into PCI memory.
*/
+static void __iomem *pci_v3_base;
+
// V3 access routines
-#define v3_writeb(o,v) __raw_writeb(v, PCI_V3_VADDR + (unsigned int)(o))
-#define v3_readb(o) (__raw_readb(PCI_V3_VADDR + (unsigned int)(o)))
+#define v3_writeb(o,v) __raw_writeb(v, pci_v3_base + (unsigned int)(o))
+#define v3_readb(o) (__raw_readb(pci_v3_base + (unsigned int)(o)))
-#define v3_writew(o,v) __raw_writew(v, PCI_V3_VADDR + (unsigned int)(o))
-#define v3_readw(o) (__raw_readw(PCI_V3_VADDR + (unsigned int)(o)))
+#define v3_writew(o,v) __raw_writew(v, pci_v3_base + (unsigned int)(o))
+#define v3_readw(o) (__raw_readw(pci_v3_base + (unsigned int)(o)))
-#define v3_writel(o,v) __raw_writel(v, PCI_V3_VADDR + (unsigned int)(o))
-#define v3_readl(o) (__raw_readl(PCI_V3_VADDR + (unsigned int)(o)))
+#define v3_writel(o,v) __raw_writel(v, pci_v3_base + (unsigned int)(o))
+#define v3_readl(o) (__raw_readl(pci_v3_base + (unsigned int)(o)))
/*============================================================================
*
return -ENODEV;
}
+ pci_v3_base = devm_ioremap(&pdev->dev, PHYS_PCI_V3_BASE, SZ_64K);
+ if (!pci_v3_base) {
+ dev_err(&pdev->dev, "unable to remap PCIv3 base\n");
+ return -ENODEV;
+ }
+
ret = devm_request_irq(&pdev->dev, IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
if (ret) {
dev_err(&pdev->dev, "unable to grab PCI error interrupt: %d\n",