KVM: PPC: Book3S PR: Emulate TIR register

In parallel to the Processor ID Register (PIR) threaded POWER8 also adds a
Thread ID Register (TIR). Since PR KVM doesn't emulate more than one thread
per core, we can just always expose 0 here.

Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
index 52448ef499cb2a78bddc48a3ee3d41651ad2f4ac..0a1de29a4caf4ddfc18490f2420097b316d2586b 100644 (file)
--- a/arch/powerpc/kvm/book3s_emulate.c
+++ b/arch/powerpc/kvm/book3s_emulate.c
@@ -566,6 +566,7 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val
        case SPRN_MMCR0:
        case SPRN_MMCR1:
        case SPRN_MMCR2:
+       case SPRN_TIR:
 #endif
                *spr_val = 0;
                break;