CONFIG_AUDIT=y
CONFIG_AUDITSYSCALL=y
CONFIG_AUDIT_TREE=y
+++++ ++
+++++ ++#
+++++ ++# RCU Subsystem
+++++ ++#
+++++ ++# CONFIG_CLASSIC_RCU is not set
+++++ ++CONFIG_TREE_RCU=y
+++++ ++# CONFIG_PREEMPT_RCU is not set
+++++ ++# CONFIG_RCU_TRACE is not set
+++++ ++CONFIG_RCU_FANOUT=32
+++++ ++# CONFIG_RCU_FANOUT_EXACT is not set
+++++ ++# CONFIG_TREE_RCU_TRACE is not set
+++++ ++# CONFIG_PREEMPT_RCU_TRACE is not set
# CONFIG_IKCONFIG is not set
- CONFIG_LOG_BUF_SHIFT=17
- CONFIG_CGROUPS=y
- # CONFIG_CGROUP_DEBUG is not set
- CONFIG_CGROUP_NS=y
- # CONFIG_CGROUP_DEVICE is not set
- CONFIG_CPUSETS=y
+ CONFIG_LOG_BUF_SHIFT=18
--- - --CONFIG_CGROUPS=y
--- - --# CONFIG_CGROUP_DEBUG is not set
--- - --CONFIG_CGROUP_NS=y
--- - --# CONFIG_CGROUP_DEVICE is not set
--- - --CONFIG_CPUSETS=y
CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
CONFIG_GROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_SMP=y
+++++ ++CONFIG_SPARSE_IRQ=y
CONFIG_X86_FIND_SMP_CONFIG=y
CONFIG_X86_MPPARSE=y
-------CONFIG_X86_PC=y
# CONFIG_X86_ELAN is not set
# CONFIG_X86_VOYAGER is not set
# CONFIG_X86_GENERICARCH is not set
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
-- --# CONFIG_EEPROM_AT24 is not set
-- --# CONFIG_EEPROM_LEGACY is not set
--- # CONFIG_AT24 is not set
--- # CONFIG_SENSORS_EEPROM is not set
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_PCF8575 is not set
# CONFIG_SENSORS_PCA9539 is not set
CONFIG_AUDIT=y
CONFIG_AUDITSYSCALL=y
CONFIG_AUDIT_TREE=y
+++++ ++
+++++ ++#
+++++ ++# RCU Subsystem
+++++ ++#
+++++ ++# CONFIG_CLASSIC_RCU is not set
+++++ ++CONFIG_TREE_RCU=y
+++++ ++# CONFIG_PREEMPT_RCU is not set
+++++ ++# CONFIG_RCU_TRACE is not set
+++++ ++CONFIG_RCU_FANOUT=64
+++++ ++# CONFIG_RCU_FANOUT_EXACT is not set
+++++ ++# CONFIG_TREE_RCU_TRACE is not set
+++++ ++# CONFIG_PREEMPT_RCU_TRACE is not set
# CONFIG_IKCONFIG is not set
- CONFIG_LOG_BUF_SHIFT=17
- CONFIG_CGROUPS=y
- # CONFIG_CGROUP_DEBUG is not set
- CONFIG_CGROUP_NS=y
- # CONFIG_CGROUP_DEVICE is not set
- CONFIG_CPUSETS=y
+ CONFIG_LOG_BUF_SHIFT=18
--- - --CONFIG_CGROUPS=y
--- - --# CONFIG_CGROUP_DEBUG is not set
--- - --CONFIG_CGROUP_NS=y
--- - --# CONFIG_CGROUP_DEVICE is not set
--- - --CONFIG_CPUSETS=y
CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
CONFIG_GROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_SMP=y
+++++ ++CONFIG_SPARSE_IRQ=y
+++++ ++# CONFIG_NUMA_MIGRATE_IRQ_DESC is not set
CONFIG_X86_FIND_SMP_CONFIG=y
CONFIG_X86_MPPARSE=y
-------CONFIG_X86_PC=y
# CONFIG_X86_ELAN is not set
# CONFIG_X86_VOYAGER is not set
# CONFIG_X86_GENERICARCH is not set
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
-- --# CONFIG_EEPROM_AT24 is not set
-- --# CONFIG_EEPROM_LEGACY is not set
--- # CONFIG_AT24 is not set
--- # CONFIG_SENSORS_EEPROM is not set
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_PCF8575 is not set
# CONFIG_SENSORS_PCA9539 is not set
#define ARCH_HAS_IOREMAP_WC
#include <linux/compiler.h>
+ #include <asm-generic/int-ll64.h>
++++++ +#include <asm/page.h>
#define build_mmio_read(name, size, type, reg, barrier) \
static inline type name(const volatile void __iomem *addr) \
#define mmiowb() barrier()
#ifdef CONFIG_X86_64
+
build_mmio_read(readq, "q", unsigned long, "=r", :"memory")
- build_mmio_read(__readq, "q", unsigned long, "=r", )
build_mmio_write(writeq, "q", unsigned long, "r", :"memory")
- build_mmio_write(__writeq, "q", unsigned long, "r", )
- #define readq_relaxed(a) __readq(a)
- #define __raw_readq __readq
- #define __raw_writeq writeq
+ #else
+
+ static inline __u64 readq(const volatile void __iomem *addr)
+ {
+ const volatile u32 __iomem *p = addr;
+ u32 low, high;
+
+ low = readl(p);
+ high = readl(p + 1);
+
+ return low + ((u64)high << 32);
+ }
+
+ static inline void writeq(__u64 val, volatile void __iomem *addr)
+ {
+ writel(val, addr);
+ writel(val >> 32, addr+4);
+ }
- /* Let people know we have them */
- #define readq readq
- #define writeq writeq
#endif
- extern int iommu_bio_merge;
+ #define readq_relaxed(a) readq(a)
+
+ #define __raw_readq(a) readq(a)
+ #define __raw_writeq(val, addr) writeq(val, addr)
+
+ /* Let people know that we have them */
+ #define readq readq
+ #define writeq writeq
+
++++++ +/**
++++++ + * virt_to_phys - map virtual addresses to physical
++++++ + * @address: address to remap
++++++ + *
++++++ + * The returned physical address is the physical (CPU) mapping for
++++++ + * the memory address given. It is only valid to use this function on
++++++ + * addresses directly mapped or allocated via kmalloc.
++++++ + *
++++++ + * This function does not give bus mappings for DMA transfers. In
++++++ + * almost all conceivable cases a device driver should not be using
++++++ + * this function
++++++ + */
++++++ +
++++++ +static inline phys_addr_t virt_to_phys(volatile void *address)
++++++ +{
++++++ + return __pa(address);
++++++ +}
++++++ +
++++++ +/**
++++++ + * phys_to_virt - map physical address to virtual
++++++ + * @address: address to remap
++++++ + *
++++++ + * The returned virtual address is a current CPU mapping for
++++++ + * the memory address given. It is only valid to use this function on
++++++ + * addresses that have a kernel mapping
++++++ + *
++++++ + * This function does not handle bus mappings for DMA transfers. In
++++++ + * almost all conceivable cases a device driver should not be using
++++++ + * this function
++++++ + */
++++++ +
++++++ +static inline void *phys_to_virt(phys_addr_t address)
++++++ +{
++++++ + return __va(address);
++++++ +}
++++++ +
++++++ +/*
++++++ + * Change "struct page" to physical address.
++++++ + */
++++++ +#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
++++++ +
++++++ +/*
++++++ + * ISA I/O bus memory addresses are 1:1 with the physical address.
++++++ + */
++++++ +#define isa_virt_to_bus virt_to_phys
++++++ +#define isa_page_to_bus page_to_phys
++++++ +#define isa_bus_to_virt phys_to_virt
++++++ +
++++++ +/*
++++++ + * However PCI ones are not necessarily 1:1 and therefore these interfaces
++++++ + * are forbidden in portable PCI drivers.
++++++ + *
++++++ + * Allow them on x86 for legacy drivers, though.
++++++ + */
++++++ +#define virt_to_bus virt_to_phys
++++++ +#define bus_to_virt phys_to_virt
++++++ +
++++++ +/**
++++++ + * ioremap - map bus memory into CPU space
++++++ + * @offset: bus address of the memory
++++++ + * @size: size of the resource to map
++++++ + *
++++++ + * ioremap performs a platform specific sequence of operations to
++++++ + * make bus memory CPU accessible via the readb/readw/readl/writeb/
++++++ + * writew/writel functions and the other mmio helpers. The returned
++++++ + * address is not guaranteed to be usable directly as a virtual
++++++ + * address.
++++++ + *
++++++ + * If the area you are trying to map is a PCI BAR you should have a
++++++ + * look at pci_iomap().
++++++ + */
++++++ +extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size);
++++++ +extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size);
++++++ +extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size,
++++++ + unsigned long prot_val);
++++++ +
++++++ +/*
++++++ + * The default ioremap() behavior is non-cached:
++++++ + */
++++++ +static inline void __iomem *ioremap(resource_size_t offset, unsigned long size)
++++++ +{
++++++ + return ioremap_nocache(offset, size);
++++++ +}
++++++ +
++++++ +extern void iounmap(volatile void __iomem *addr);
++++++ +
++++++ +extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys);
++++++ +
+++ ++ +
#ifdef CONFIG_X86_32
# include "io_32.h"
#else
#define pte_pgprot(x) __pgprot(pte_flags(x) & PTE_FLAGS_MASK)
---- --#define canon_pgprot(p) __pgprot(pgprot_val(p) & __supported_pte_mask)
++++ ++#define canon_pgprot(p) __pgprot(massage_pgprot(p))
++
++ static inline int is_new_memtype_allowed(unsigned long flags,
++ unsigned long new_flags)
++ {
++ /*
++ * Certain new memtypes are not allowed with certain
++ * requested memtype:
++ * - request is uncached, return cannot be write-back
++ * - request is write-combine, return cannot be write-back
++ */
++ if ((flags == _PAGE_CACHE_UC_MINUS &&
++ new_flags == _PAGE_CACHE_WB) ||
++ (flags == _PAGE_CACHE_WC &&
++ new_flags == _PAGE_CACHE_WB)) {
++ return 0;
++ }
++
++ return 1;
++ }
#ifndef __ASSEMBLY__
+ /* Indicate that x86 has its own track and untrack pfn vma functions */
+ #define __HAVE_PFNMAP_TRACKING
+
#define __HAVE_PHYS_MEM_ACCESS_PROT
struct file;
pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
#ifndef __ASSEMBLY__
------ -static inline int pgd_bad(pgd_t pgd)
------ -{
------ - return (pgd_val(pgd) & ~(PTE_PFN_MASK | _PAGE_USER)) != _KERNPG_TABLE;
------ -}
------ -
------ -static inline int pud_bad(pud_t pud)
------ -{
------ - return (pud_val(pud) & ~(PTE_PFN_MASK | _PAGE_USER)) != _KERNPG_TABLE;
------ -}
------ -
------ -static inline int pmd_bad(pmd_t pmd)
------ -{
------ - return (pmd_val(pmd) & ~(PTE_PFN_MASK | _PAGE_USER)) != _KERNPG_TABLE;
------ -}
------ -
------ -#define pte_none(x) (!pte_val((x)))
------ -#define pte_present(x) (pte_val((x)) & (_PAGE_PRESENT | _PAGE_PROTNONE))
------ -
------ -#define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT)) /* FIXME: is this right? */
-
- /*
- * Macro to mark a page protection value as "uncacheable".
- */
- #define pgprot_noncached(prot) \
- (__pgprot(pgprot_val((prot)) | _PAGE_PCD | _PAGE_PWT))
------ -
/*
* Conversion functions: convert a page and protection to a page entry,
* and a page entry and page directory to the page they refer to.
#include <asm/mpspec.h>
#include <asm/smp.h>
-------#ifdef CONFIG_X86_LOCAL_APIC
-------# include <mach_apic.h>
-------#endif
-------
static int __initdata acpi_force = 0;
-
+ u32 acpi_rsdt_forced;
#ifdef CONFIG_ACPI
int acpi_disabled = 0;
#else
if (!phys || !size)
return NULL;
- ------ if (phys+size <= (max_low_pfn_mapped << PAGE_SHIFT))
- ------ return __va(phys);
- ------
- ------ offset = phys & (PAGE_SIZE - 1);
- ------ mapped_size = PAGE_SIZE - offset;
- ------ clear_fixmap(FIX_ACPI_END);
- ------ set_fixmap(FIX_ACPI_END, phys);
- ------ base = fix_to_virt(FIX_ACPI_END);
- ------
- ------ /*
- ------ * Most cases can be covered by the below.
- ------ */
- ------ idx = FIX_ACPI_END;
- ------ while (mapped_size < size) {
- ------ if (--idx < FIX_ACPI_BEGIN)
- ------ return NULL; /* cannot handle this */
- ------ phys += PAGE_SIZE;
- ------ clear_fixmap(idx);
- ------ set_fixmap(idx, phys);
- ------ mapped_size += PAGE_SIZE;
- ------ }
-
- return ((unsigned char *)base + offset);
+ ++++++ return early_ioremap(phys, size);
+ ++++++}
+ ++++++void __init __acpi_unmap_table(char *map, unsigned long size)
+ ++++++{
+ ++++++ if (!map || !size)
+ ++++++ return;
+
------ return ((unsigned char *)base + offset);
+ ++++++ early_iounmap(map, size);
}
#ifdef CONFIG_PCI_MMCONFIG
nr_ioapics++;
}
---- --static void assign_to_mp_irq(struct mp_config_intsrc *m,
---- -- struct mp_config_intsrc *mp_irq)
++++ ++int __init acpi_probe_gsi(void)
{
---- -- memcpy(mp_irq, m, sizeof(struct mp_config_intsrc));
++++ ++ int idx;
++++ ++ int gsi;
++++ ++ int max_gsi = 0;
++++ ++
++++ ++ if (acpi_disabled)
++++ ++ return 0;
++++ ++
++++ ++ if (!acpi_ioapic)
++++ ++ return 0;
++++ ++
++++ ++ max_gsi = 0;
++++ ++ for (idx = 0; idx < nr_ioapics; idx++) {
++++ ++ gsi = mp_ioapic_routing[idx].gsi_end;
++++ ++
++++ ++ if (gsi > max_gsi)
++++ ++ max_gsi = gsi;
++++ ++ }
++++ ++
++++ ++ return max_gsi + 1;
}
---- --static int mp_irq_cmp(struct mp_config_intsrc *mp_irq,
---- -- struct mp_config_intsrc *m)
- static void assign_to_mp_irq(struct mp_config_intsrc *m,
- struct mp_config_intsrc *mp_irq)
+++++++static void assign_to_mp_irq(struct mpc_intsrc *m,
+++++++ struct mpc_intsrc *mp_irq)
{
---- -- return memcmp(mp_irq, m, sizeof(struct mp_config_intsrc));
- memcpy(mp_irq, m, sizeof(struct mp_config_intsrc));
+++++++ memcpy(mp_irq, m, sizeof(struct mpc_intsrc));
}
---- --static void save_mp_irq(struct mp_config_intsrc *m)
- static int mp_irq_cmp(struct mp_config_intsrc *mp_irq,
- struct mp_config_intsrc *m)
+++++++static int mp_irq_cmp(struct mpc_intsrc *mp_irq,
+++++++ struct mpc_intsrc *m)
++++ ++{
- return memcmp(mp_irq, m, sizeof(struct mp_config_intsrc));
+++++++ return memcmp(mp_irq, m, sizeof(struct mpc_intsrc));
++++ ++}
++++ ++
- static void save_mp_irq(struct mp_config_intsrc *m)
+++++++static void save_mp_irq(struct mpc_intsrc *m)
{
int i;
* Mikael Pettersson : PM converted to driver model.
*/
-------#include <linux/init.h>
-------
-------#include <linux/mm.h>
-------#include <linux/delay.h>
-------#include <linux/bootmem.h>
-------#include <linux/interrupt.h>
-------#include <linux/mc146818rtc.h>
#include <linux/kernel_stat.h>
-------#include <linux/sysdev.h>
-------#include <linux/ioport.h>
-------#include <linux/cpu.h>
-------#include <linux/clockchips.h>
+++++++#include <linux/mc146818rtc.h>
#include <linux/acpi_pmtmr.h>
+++++++#include <linux/clockchips.h>
+++++++#include <linux/interrupt.h>
+++++++#include <linux/bootmem.h>
+++++++#include <linux/ftrace.h>
+++++++#include <linux/ioport.h>
#include <linux/module.h>
-------#include <linux/dmi.h>
+++++++#include <linux/sysdev.h>
+++++++#include <linux/delay.h>
+++++++#include <linux/timex.h>
#include <linux/dmar.h>
-- ----#include <linux/ftrace.h>
-- ----#include <linux/smp.h>
+++++++#include <linux/init.h>
+++++++#include <linux/cpu.h>
+++++++#include <linux/dmi.h>
+ #include <linux/nmi.h>
-- ----#include <linux/timex.h>
+++++++#include <linux/smp.h>
+++++++#include <linux/mm.h>
-------#include <asm/atomic.h>
- #include <asm/smp.h>
-------#include <asm/mtrr.h>
-------#include <asm/mpspec.h>
-------#include <asm/desc.h>
#include <asm/arch_hooks.h>
-------#include <asm/hpet.h>
#include <asm/pgalloc.h>
+++++++#include <asm/genapic.h>
+++++++#include <asm/atomic.h>
+++++++#include <asm/mpspec.h>
#include <asm/i8253.h>
- #include <asm/nmi.h>
-------#include <asm/idle.h>
+++++++#include <asm/i8259.h>
#include <asm/proto.h>
- #include <asm/timex.h>
#include <asm/apic.h>
-------#include <asm/i8259.h>
+++++++#include <asm/desc.h>
+++++++#include <asm/hpet.h>
+++++++#include <asm/idle.h>
+++++++#include <asm/mtrr.h>
++ #include <asm/smp.h>
++
- ----#include <mach_apic.h>
- ----#include <mach_apicdef.h>
- ----#include <mach_ipi.h>
+++++++unsigned int num_processors;
+++++++
+++++++unsigned disabled_cpus __cpuinitdata;
+ +++++
- #include <mach_apic.h>
- #include <mach_apicdef.h>
- #include <mach_ipi.h>
+++++++/* Processor that is doing the boot up */
+++++++unsigned int boot_cpu_physical_apicid = -1U;
- #include <mach_apic.h>
- #include <mach_apicdef.h>
- #include <mach_ipi.h>
+ /*
-- ---- * Sanity check
+++++++ * The highest APIC ID seen during enumeration.
+++++++ *
+++++++ * This determines the messaging protocol we can use: if all APIC IDs
+++++++ * are in the 0 ... 7 range, then we can use logical addressing which
+++++++ * has some performance advantages (better broadcasting).
+++++++ *
+++++++ * If there's an APIC ID above 8, we use physical addressing.
+ */
-- ----#if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
-- ----# error SPURIOUS_APIC_VECTOR definition error
-- ----#endif
+++++++unsigned int max_physical_apicid;
++ ++++
++ ++++/*
- * Sanity check
+++++++ * Bitmask of physically existing CPUs:
++ ++++ */
- #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
- # error SPURIOUS_APIC_VECTOR definition error
- #endif
+++++++physid_mask_t phys_cpu_present_map;
+++++++
+++++++/*
+++++++ * Map cpu index to physical APIC ID
+++++++ */
+++++++DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
+++++++DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
+++++++EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
+++++++EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
#ifdef CONFIG_X86_32
/*
/*
* Local APIC timer broadcast function
*/
- static void lapic_timer_broadcast(cpumask_t mask)
+ static void lapic_timer_broadcast(const struct cpumask *mask)
{
#ifdef CONFIG_SMP
------- send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
+++++++ apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
#endif
}
if (deltapm > (pm_100ms - pm_thresh) &&
deltapm < (pm_100ms + pm_thresh)) {
------- apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
------- } else {
------- res = (((u64)deltapm) * mult) >> 22;
------- do_div(res, 1000000);
--- --- pr_warning("APIC calibration not consistent "
- printk(KERN_WARNING "APIC calibration not consistent "
------- "with PM Timer: %ldms instead of 100ms\n",
------- (long)res);
------- /* Correct the lapic counter value */
------- res = (((u64)(*delta)) * pm_100ms);
+++++++ apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
+++++++ return 0;
+++++++ }
+++++++
+++++++ res = (((u64)deltapm) * mult) >> 22;
+++++++ do_div(res, 1000000);
+++++++ pr_warning("APIC calibration not consistent "
+++++++ "with PM-Timer: %ldms instead of 100ms\n",(long)res);
+++++++
+++++++ /* Correct the lapic counter value */
+++++++ res = (((u64)(*delta)) * pm_100ms);
+++++++ do_div(res, deltapm);
+++++++ pr_info("APIC delta adjusted to PM-Timer: "
+++++++ "%lu (%ld)\n", (unsigned long)res, *delta);
+++++++ *delta = (long)res;
+++++++
+++++++ /* Correct the tsc counter value */
+++++++ if (cpu_has_tsc) {
+++++++ res = (((u64)(*deltatsc)) * pm_100ms);
do_div(res, deltapm);
--- --- pr_info("APIC delta adjusted to PM-Timer: "
- printk(KERN_INFO "APIC delta adjusted to PM-Timer: "
------- "%lu (%ld)\n", (unsigned long)res, *delta);
------- *delta = (long)res;
+++++++ apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
+++++++ "PM-Timer: %lu (%ld) \n",
+++++++ (unsigned long)res, *deltatsc);
+++++++ *deltatsc = (long)res;
}
return 0;
int __init APIC_init_uniprocessor(void)
{
-------#ifdef CONFIG_X86_64
if (disable_apic) {
- printk(KERN_INFO "Apic disabled\n");
+ pr_info("Apic disabled\n");
return -1;
}
+++++++#ifdef CONFIG_X86_64
if (!cpu_has_apic) {
disable_apic = 1;
- printk(KERN_INFO "Apic disabled by BIOS\n");
+ pr_info("Apic disabled by BIOS\n");
return -1;
}
#else
}
num_processors++;
- cpus_complement(tmp_map, cpu_present_map);
- cpu = first_cpu(tmp_map);
+ cpu = cpumask_next_zero(-1, cpu_present_mask);
+
+++ if (version != apic_version[boot_cpu_physical_apicid])
+++ WARN_ONCE(1,
+++ "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
+++ apic_version[boot_cpu_physical_apicid], cpu, version);
+ +
physid_set(apicid, phys_cpu_present_map);
if (apicid == boot_cpu_physical_apicid) {
/*
}
#endif
-------#if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
------- /* are we being called early in kernel startup? */
------- if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
------- u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
------- u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
-------
------- cpu_to_apicid[cpu] = apicid;
------- bios_cpu_apicid[cpu] = apicid;
------- } else {
------- per_cpu(x86_cpu_to_apicid, cpu) = apicid;
------- per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
------- }
+++++++#if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
+++++++ early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
+++++++ early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
#endif
- cpu_set(cpu, cpu_possible_map);
- cpu_set(cpu, cpu_present_map);
+ set_cpu_possible(cpu, true);
+ set_cpu_present(cpu, true);
}
-------#ifdef CONFIG_X86_64
int hard_smp_processor_id(void)
{
return read_apic_id();
#include <asm/io.h>
#include <asm/nmi.h>
#include <asm/smp.h>
+ #include <asm/atomic.h>
#include <asm/apicdef.h>
-------#include <mach_mpparse.h>
+ #include <asm/genapic.h>
+ #include <asm/setup.h>
/*
* ES7000 chipsets
return gsi;
}
-- ----static void noop_wait_for_deassert(atomic_t *deassert_not_used)
-- ----{
-- ----}
-- ----
+ static int wakeup_secondary_cpu_via_mip(int cpu, unsigned long eip)
+ {
+ unsigned long vect = 0, psaival = 0;
+
+ if (psai == NULL)
+ return -1;
+
+ vect = ((unsigned long)__pa(eip)/0x1000) << 16;
+ psaival = (0x1000000 | vect | cpu);
+
+ while (*psai & 0x1000000)
+ ;
+
+ *psai = psaival;
+
+ return 0;
+ }
+
-- ---- genapic->wakeup_cpu = wakeup_secondary_cpu_via_mip;
+ static int __init es7000_update_genapic(void)
+ {
-- ---- genapic->wait_for_init_deassert = noop_wait_for_deassert;
-- ---- genapic->wakeup_cpu = wakeup_secondary_cpu_via_mip;
+++++++ apic->wakeup_cpu = wakeup_secondary_cpu_via_mip;
+
+ /* MPENTIUMIII */
+ if (boot_cpu_data.x86 == 6 &&
+ (boot_cpu_data.x86_model >= 7 || boot_cpu_data.x86_model <= 11)) {
+ es7000_update_genapic_to_cluster();
+++++++ apic->wait_for_init_deassert = NULL;
+++++++ apic->wakeup_cpu = wakeup_secondary_cpu_via_mip;
+ }
+
+ return 0;
+ }
+
void __init
setup_unisys(void)
{
return status;
}
-- ----void __init
-- ----es7000_sw_apic(void)
-- ----{
-- ---- if (es7000_plat) {
-- ---- int mip_status;
-- ---- struct mip_reg es7000_mip_reg;
-- ----
-- ---- printk("ES7000: Enabling APIC mode.\n");
-- ---- memset(&es7000_mip_reg, 0, sizeof(struct mip_reg));
-- ---- es7000_mip_reg.off_0 = MIP_SW_APIC;
-- ---- es7000_mip_reg.off_38 = (MIP_VALID);
-- ---- while ((mip_status = es7000_mip_write(&es7000_mip_reg)) != 0)
-- ---- printk("es7000_sw_apic: command failed, status = %x\n",
-- ---- mip_status);
- int
- es7000_start_cpu(int cpu, unsigned long eip)
+++++++void __init es7000_enable_apic_mode(void)
++ ++++{
- unsigned long vect = 0, psaival = 0;
+++++++ struct mip_reg es7000_mip_reg;
+++++++ int mip_status;
++ ++++
- if (psai == NULL)
- return -1;
+++++++ if (!es7000_plat)
+ return;
++ ++++
- vect = ((unsigned long)__pa(eip)/0x1000) << 16;
- psaival = (0x1000000 | vect | cpu);
+++++++ printk("ES7000: Enabling APIC mode.\n");
+++++++ memset(&es7000_mip_reg, 0, sizeof(struct mip_reg));
+++++++ es7000_mip_reg.off_0 = MIP_SW_APIC;
+++++++ es7000_mip_reg.off_38 = MIP_VALID;
++ ++++
- while (*psai & 0x1000000)
- ;
+++++++ while ((mip_status = es7000_mip_write(&es7000_mip_reg)) != 0) {
+++++++ printk("es7000_enable_apic_mode: command failed, status = %x\n",
+++++++ mip_status);
+++++++ }
+++++++}
+++++++
+++++++/*
+++++++ * APIC driver for the Unisys ES7000 chipset.
+++++++ */
+++++++#define APIC_DEFINITION 1
+++++++#include <linux/threads.h>
+++++++#include <linux/cpumask.h>
+++++++#include <asm/mpspec.h>
+++++++#include <asm/genapic.h>
+++++++#include <asm/fixmap.h>
+++++++#include <asm/apicdef.h>
+++++++#include <linux/kernel.h>
+++++++#include <linux/string.h>
+++++++#include <linux/init.h>
+++++++#include <linux/acpi.h>
+++++++#include <linux/smp.h>
+++++++#include <asm/ipi.h>
+++++++
+++++++#define APIC_DFR_VALUE_CLUSTER (APIC_DFR_CLUSTER)
+++++++#define INT_DELIVERY_MODE_CLUSTER (dest_LowestPrio)
+++++++#define INT_DEST_MODE_CLUSTER (1) /* logical delivery broadcast to all procs */
+++++++
+++++++#define APIC_DFR_VALUE (APIC_DFR_FLAT)
+++++++
+++++++extern void es7000_enable_apic_mode(void);
+++++++extern int apic_version [MAX_APICS];
+++++++extern u8 cpu_2_logical_apicid[];
+++++++extern unsigned int boot_cpu_physical_apicid;
+++++++
+++++++extern int parse_unisys_oem (char *oemptr);
+++++++extern int find_unisys_acpi_oem_table(unsigned long *oem_addr);
+++++++extern void unmap_unisys_acpi_oem_table(unsigned long oem_addr);
+++++++extern void setup_unisys(void);
+++++++
+++++++#define apicid_cluster(apicid) (apicid & 0xF0)
+++++++#define xapic_phys_to_log_apicid(cpu) per_cpu(x86_bios_cpu_apicid, cpu)
+++++++
+++++++static void es7000_vector_allocation_domain(int cpu, cpumask_t *retmask)
+++++++{
+++++++ /* Careful. Some cpus do not strictly honor the set of cpus
+++++++ * specified in the interrupt destination when using lowest
+++++++ * priority interrupt delivery mode.
+++++++ *
+++++++ * In particular there was a hyperthreading cpu observed to
+++++++ * deliver interrupts to the wrong hyperthread when only one
+++++++ * hyperthread was specified in the interrupt desitination.
+++++++ */
+++++++ *retmask = (cpumask_t){ { [0] = APIC_ALL_CPUS, } };
+++++++}
++ ++++
- *psai = psaival;
++ ++++
+++++++static void es7000_wait_for_init_deassert(atomic_t *deassert)
+++++++{
+++++++#ifndef CONFIG_ES7000_CLUSTERED_APIC
+++++++ while (!atomic_read(deassert))
+++++++ cpu_relax();
+++++++#endif
+++++++ return;
+++++++}
+++++++
+++++++static unsigned int es7000_get_apic_id(unsigned long x)
+++++++{
+++++++ return (x >> 24) & 0xFF;
+++++++}
+++++++
+++++++#ifdef CONFIG_ACPI
+++++++static int es7000_check_dsdt(void)
+++++++{
+++++++ struct acpi_table_header header;
+++++++
+++++++ if (ACPI_SUCCESS(acpi_get_table_header(ACPI_SIG_DSDT, 0, &header)) &&
+++++++ !strncmp(header.oem_id, "UNISYS", 6))
+++++++ return 1;
++ ++++ return 0;
+++++++}
+++++++#endif
++ ++++
+++++++static void es7000_send_IPI_mask(const struct cpumask *mask, int vector)
+++++++{
+++++++ default_send_IPI_mask_sequence_phys(mask, vector);
++ ++++}
++ ++++
- void __init
- es7000_sw_apic(void)
- {
- if (es7000_plat) {
- int mip_status;
- struct mip_reg es7000_mip_reg;
-
- printk("ES7000: Enabling APIC mode.\n");
- memset(&es7000_mip_reg, 0, sizeof(struct mip_reg));
- es7000_mip_reg.off_0 = MIP_SW_APIC;
- es7000_mip_reg.off_38 = (MIP_VALID);
- while ((mip_status = es7000_mip_write(&es7000_mip_reg)) != 0)
- printk("es7000_sw_apic: command failed, status = %x\n",
- mip_status);
- return;
+++++++static void es7000_send_IPI_allbutself(int vector)
+++++++{
+++++++ default_send_IPI_mask_allbutself_phys(cpu_online_mask, vector);
+++++++}
+++++++
+++++++static void es7000_send_IPI_all(int vector)
+++++++{
+++++++ es7000_send_IPI_mask(cpu_online_mask, vector);
+++++++}
+++++++
+++++++static int es7000_apic_id_registered(void)
+++++++{
+++++++ return 1;
+++++++}
+++++++
+++++++static const cpumask_t *target_cpus_cluster(void)
+++++++{
+++++++ return &CPU_MASK_ALL;
+++++++}
+++++++
+++++++static const cpumask_t *es7000_target_cpus(void)
+++++++{
+++++++ return &cpumask_of_cpu(smp_processor_id());
+++++++}
+++++++
+++++++static unsigned long
+++++++es7000_check_apicid_used(physid_mask_t bitmap, int apicid)
+++++++{
+++++++ return 0;
+++++++}
+++++++static unsigned long es7000_check_apicid_present(int bit)
+++++++{
+++++++ return physid_isset(bit, phys_cpu_present_map);
+++++++}
+++++++
+++++++static unsigned long calculate_ldr(int cpu)
+++++++{
+++++++ unsigned long id = xapic_phys_to_log_apicid(cpu);
+++++++
+++++++ return (SET_APIC_LOGICAL_ID(id));
+++++++}
+++++++
+++++++/*
+++++++ * Set up the logical destination ID.
+++++++ *
+++++++ * Intel recommends to set DFR, LdR and TPR before enabling
+++++++ * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
+++++++ * document number 292116). So here it goes...
+++++++ */
+++++++static void es7000_init_apic_ldr_cluster(void)
+++++++{
+++++++ unsigned long val;
+++++++ int cpu = smp_processor_id();
+++++++
+++++++ apic_write(APIC_DFR, APIC_DFR_VALUE_CLUSTER);
+++++++ val = calculate_ldr(cpu);
+++++++ apic_write(APIC_LDR, val);
+++++++}
+++++++
+++++++static void es7000_init_apic_ldr(void)
+++++++{
+++++++ unsigned long val;
+++++++ int cpu = smp_processor_id();
+++++++
+++++++ apic_write(APIC_DFR, APIC_DFR_VALUE);
+++++++ val = calculate_ldr(cpu);
+++++++ apic_write(APIC_LDR, val);
+++++++}
+++++++
+++++++static void es7000_setup_apic_routing(void)
+++++++{
+++++++ int apic = per_cpu(x86_bios_cpu_apicid, smp_processor_id());
+++++++ printk("Enabling APIC mode: %s. Using %d I/O APICs, target cpus %lx\n",
+++++++ (apic_version[apic] == 0x14) ?
+++++++ "Physical Cluster" : "Logical Cluster",
+++++++ nr_ioapics, cpus_addr(*es7000_target_cpus())[0]);
+++++++}
+++++++
+++++++static int es7000_apicid_to_node(int logical_apicid)
+++++++{
+++++++ return 0;
+++++++}
+++++++
+++++++
+++++++static int es7000_cpu_present_to_apicid(int mps_cpu)
+++++++{
+++++++ if (!mps_cpu)
+++++++ return boot_cpu_physical_apicid;
+++++++ else if (mps_cpu < nr_cpu_ids)
+++++++ return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu);
+++++++ else
+++++++ return BAD_APICID;
+++++++}
+++++++
+++++++static physid_mask_t es7000_apicid_to_cpu_present(int phys_apicid)
+++++++{
+++++++ static int id = 0;
+++++++ physid_mask_t mask;
+++++++
+++++++ mask = physid_mask_of_physid(id);
+++++++ ++id;
+++++++
+++++++ return mask;
+++++++}
+++++++
+++++++/* Mapping from cpu number to logical apicid */
+++++++static int es7000_cpu_to_logical_apicid(int cpu)
+++++++{
+++++++#ifdef CONFIG_SMP
+++++++ if (cpu >= nr_cpu_ids)
+++++++ return BAD_APICID;
+++++++ return (int)cpu_2_logical_apicid[cpu];
+++++++#else
+++++++ return logical_smp_processor_id();
+++++++#endif
+++++++}
+++++++
+++++++static physid_mask_t es7000_ioapic_phys_id_map(physid_mask_t phys_map)
+++++++{
+++++++ /* For clustered we don't have a good way to do this yet - hack */
+++++++ return physids_promote(0xff);
+++++++}
+++++++
+++++++static int es7000_check_phys_apicid_present(int cpu_physical_apicid)
+++++++{
+++++++ boot_cpu_physical_apicid = read_apic_id();
+++++++ return (1);
+++++++}
+++++++
+++++++static unsigned int
+++++++es7000_cpu_mask_to_apicid_cluster(const struct cpumask *cpumask)
+++++++{
+++++++ int cpus_found = 0;
+++++++ int num_bits_set;
+++++++ int apicid;
+++++++ int cpu;
+++++++
+++++++ num_bits_set = cpumask_weight(cpumask);
+++++++ /* Return id to all */
+++++++ if (num_bits_set == nr_cpu_ids)
+++++++ return 0xFF;
+++++++ /*
+++++++ * The cpus in the mask must all be on the apic cluster. If are not
+++++++ * on the same apicid cluster return default value of target_cpus():
+++++++ */
+++++++ cpu = cpumask_first(cpumask);
+++++++ apicid = es7000_cpu_to_logical_apicid(cpu);
+++++++
+++++++ while (cpus_found < num_bits_set) {
+++++++ if (cpumask_test_cpu(cpu, cpumask)) {
+++++++ int new_apicid = es7000_cpu_to_logical_apicid(cpu);
+++++++
+++++++ if (apicid_cluster(apicid) !=
+++++++ apicid_cluster(new_apicid)) {
+++++++ printk ("%s: Not a valid mask!\n", __func__);
+++++++
+++++++ return 0xFF;
+++++++ }
+++++++ apicid = new_apicid;
+++++++ cpus_found++;
+++++++ }
+++++++ cpu++;
++++++ }
+++++++ return apicid;
++++++}
+++++++
+++++++static unsigned int es7000_cpu_mask_to_apicid(const cpumask_t *cpumask)
+++++++{
+++++++ int cpus_found = 0;
+++++++ int num_bits_set;
+++++++ int apicid;
+++++++ int cpu;
+++++++
+++++++ num_bits_set = cpus_weight(*cpumask);
+++++++ /* Return id to all */
+++++++ if (num_bits_set == nr_cpu_ids)
+++++++ return es7000_cpu_to_logical_apicid(0);
+++++++ /*
+++++++ * The cpus in the mask must all be on the apic cluster. If are not
+++++++ * on the same apicid cluster return default value of target_cpus():
+++++++ */
+++++++ cpu = first_cpu(*cpumask);
+++++++ apicid = es7000_cpu_to_logical_apicid(cpu);
+++++++ while (cpus_found < num_bits_set) {
+++++++ if (cpu_isset(cpu, *cpumask)) {
+++++++ int new_apicid = es7000_cpu_to_logical_apicid(cpu);
+++++++
+++++++ if (apicid_cluster(apicid) !=
+++++++ apicid_cluster(new_apicid)) {
+++++++ printk ("%s: Not a valid mask!\n", __func__);
+++++++
+++++++ return es7000_cpu_to_logical_apicid(0);
+++++++ }
+++++++ apicid = new_apicid;
+++++++ cpus_found++;
+++++++ }
+++++++ cpu++;
++ ++++ }
+++++++ return apicid;
++ ++++}
+++++++
+++++++static unsigned int
+++++++es7000_cpu_mask_to_apicid_and(const struct cpumask *inmask,
+++++++ const struct cpumask *andmask)
+++++++{
+++++++ int apicid = es7000_cpu_to_logical_apicid(0);
+++++++ cpumask_var_t cpumask;
+++++++
+++++++ if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC))
+++++++ return apicid;
+++++++
+++++++ cpumask_and(cpumask, inmask, andmask);
+++++++ cpumask_and(cpumask, cpumask, cpu_online_mask);
+++++++ apicid = es7000_cpu_mask_to_apicid(cpumask);
+++++++
+++++++ free_cpumask_var(cpumask);
+++++++
+++++++ return apicid;
+++++++}
+++++++
+++++++static int es7000_phys_pkg_id(int cpuid_apic, int index_msb)
+++++++{
+++++++ return cpuid_apic >> index_msb;
+++++++}
+++++++
+++++++void __init es7000_update_genapic_to_cluster(void)
+++++++{
+++++++ apic->target_cpus = target_cpus_cluster;
+++++++ apic->irq_delivery_mode = INT_DELIVERY_MODE_CLUSTER;
+++++++ apic->irq_dest_mode = INT_DEST_MODE_CLUSTER;
+++++++
+++++++ apic->init_apic_ldr = es7000_init_apic_ldr_cluster;
+++++++
+++++++ apic->cpu_mask_to_apicid = es7000_cpu_mask_to_apicid_cluster;
+++++++}
+++++++
+++++++static int probe_es7000(void)
+++++++{
+++++++ /* probed later in mptable/ACPI hooks */
+++++++ return 0;
+++++++}
+++++++
+++++++static __init int
+++++++es7000_mps_oem_check(struct mpc_table *mpc, char *oem, char *productid)
+++++++{
+++++++ if (mpc->oemptr) {
+++++++ struct mpc_oemtable *oem_table =
+++++++ (struct mpc_oemtable *)mpc->oemptr;
+++++++
+++++++ if (!strncmp(oem, "UNISYS", 6))
+++++++ return parse_unisys_oem((char *)oem_table);
+++++++ }
+++++++ return 0;
+++++++}
+++++++
+++++++#ifdef CONFIG_ACPI
+++++++/* Hook from generic ACPI tables.c */
+++++++static int __init es7000_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
+++++++{
+++++++ unsigned long oem_addr = 0;
+++++++ int check_dsdt;
+++++++ int ret = 0;
+++++++
+++++++ /* check dsdt at first to avoid clear fix_map for oem_addr */
+++++++ check_dsdt = es7000_check_dsdt();
+++++++
+++++++ if (!find_unisys_acpi_oem_table(&oem_addr)) {
+++++++ if (check_dsdt)
+++++++ ret = parse_unisys_oem((char *)oem_addr);
+++++++ else {
+++++++ setup_unisys();
+++++++ ret = 1;
+++++++ }
+++++++ /*
+++++++ * we need to unmap it
+++++++ */
+++++++ unmap_unisys_acpi_oem_table(oem_addr);
+ + }
+++++++ return ret;
+++++++}
+++++++#else
+++++++static int __init es7000_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
+++++++{
+++++++ return 0;
+ + }
+++++++#endif
+++++++
+++++++
+++++++struct genapic apic_es7000 = {
+++++++
+++++++ .name = "es7000",
+++++++ .probe = probe_es7000,
+++++++ .acpi_madt_oem_check = es7000_acpi_madt_oem_check,
+++++++ .apic_id_registered = es7000_apic_id_registered,
+++++++
+++++++ .irq_delivery_mode = dest_Fixed,
+++++++ /* phys delivery to target CPUs: */
+++++++ .irq_dest_mode = 0,
+++++++
+++++++ .target_cpus = es7000_target_cpus,
+++++++ .disable_esr = 1,
+++++++ .dest_logical = 0,
+++++++ .check_apicid_used = es7000_check_apicid_used,
+++++++ .check_apicid_present = es7000_check_apicid_present,
+++++++
+++++++ .vector_allocation_domain = es7000_vector_allocation_domain,
+++++++ .init_apic_ldr = es7000_init_apic_ldr,
+++++++
+++++++ .ioapic_phys_id_map = es7000_ioapic_phys_id_map,
+++++++ .setup_apic_routing = es7000_setup_apic_routing,
+++++++ .multi_timer_check = NULL,
+++++++ .apicid_to_node = es7000_apicid_to_node,
+++++++ .cpu_to_logical_apicid = es7000_cpu_to_logical_apicid,
+++++++ .cpu_present_to_apicid = es7000_cpu_present_to_apicid,
+++++++ .apicid_to_cpu_present = es7000_apicid_to_cpu_present,
+++++++ .setup_portio_remap = NULL,
+++++++ .check_phys_apicid_present = es7000_check_phys_apicid_present,
+++++++ .enable_apic_mode = es7000_enable_apic_mode,
+++++++ .phys_pkg_id = es7000_phys_pkg_id,
+++++++ .mps_oem_check = es7000_mps_oem_check,
+++++++
+++++++ .get_apic_id = es7000_get_apic_id,
+++++++ .set_apic_id = NULL,
+++++++ .apic_id_mask = 0xFF << 24,
+++++++
+++++++ .cpu_mask_to_apicid = es7000_cpu_mask_to_apicid,
+++++++ .cpu_mask_to_apicid_and = es7000_cpu_mask_to_apicid_and,
+++++++
+++++++ .send_IPI_mask = es7000_send_IPI_mask,
+++++++ .send_IPI_mask_allbutself = NULL,
+++++++ .send_IPI_allbutself = es7000_send_IPI_allbutself,
+++++++ .send_IPI_all = es7000_send_IPI_all,
+++++++ .send_IPI_self = default_send_IPI_self,
+++++++
+++++++ .wakeup_cpu = NULL,
+++++++
+++++++ .trampoline_phys_low = 0x467,
+++++++ .trampoline_phys_high = 0x469,
+++++++
+++++++ .wait_for_init_deassert = es7000_wait_for_init_deassert,
+++++++
+++++++ /* Nothing to do for most platforms, since cleared by the INIT cycle: */
+++++++ .smp_callin_clear_local_apic = NULL,
+++++++ .store_NMI_vector = NULL,
+++++++ .inquire_remote_apic = default_inquire_remote_apic,
+++++++};
projects / GitHub / exynos8895 / android_kernel_samsung_universal8895.git / commitdiff