[9610] dtsi: add sysmmu properties

Change-Id: Ie855f0baa5cfec54c5950203398d010be7613fdc
Signed-off-by: Janghyuck Kim <janghyuck.kim@samsung.com>

diff --git a/arch/arm64/boot/dts/exynos/exynos9610-sysmmu.dtsi b/arch/arm64/boot/dts/exynos/exynos9610-sysmmu.dtsi
index 75af2cb9da00e77cd9a6b0081f0d1f1a1113bf7b..bfb4fd7b9b2d6f3582d14550e5c6c5d3633d669e 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos9610-sysmmu.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos9610-sysmmu.dtsi
@@ -23,16 +23,14 @@
                reg = <0x0 0x10C50000 0x9000>;
                interrupts = <0 127 0>,
                             <0 128 0>;
-               /*
+               qos = <15>;
                clock-names = "aclk";
-               clocks = <&clock GATE_SMMU_XXX>;
-                */
+               clocks = <&clock GATE_SMMU_D_VIPX1_QCH>;
                port-name = "VIPX";
                sysmmu,secure-irq;
                sysmmu,secure_base = <0x10C40000>;
-               /*
                sysmmu,tlb_property =
-                */
+                       <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL8) SYSMMU_NOID>;
                #iommu-cells = <0>;
        };
 
@@ -41,16 +39,14 @@
                reg = <0x0 0x10E50000 0x9000>;
                interrupts = <0 371 0>,
                             <0 372 0>;
-               /*
+               qos = <15>;
                clock-names = "aclk";
-               clocks = <&clock GATE_SMMU_XXX>;
-                */
+               clocks = <&clock GATE_SMMU_D_VIPX2_QCH>;
                port-name = "VIPX";
                sysmmu,secure-irq;
                sysmmu,secure_base = <0x10E40000>;
-               /*
                sysmmu,tlb_property =
-                */
+                       <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL8) SYSMMU_NOID>;
                #iommu-cells = <0>;
        };
 
@@ -59,16 +55,14 @@
                reg = <0x0 0x12C70000 0x9000>;
                interrupts = <0 181 0>,
                             <0 182 0>;
-               /*
+               qos = <15>;
                clock-names = "aclk";
-               clocks = <&clock GATE_SMMU_XXX>;
-                */
+               clocks = <&clock GATE_SYSMMU_MFCD0_QCH>;
                port-name = "MFC0";
                sysmmu,secure-irq;
                sysmmu,secure_base = <0x12C80000>;
-               /*
                sysmmu,tlb_property =
-                */
+                       <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL8) SYSMMU_NOID>;
                #iommu-cells = <0>;
        };
 
@@ -77,16 +71,15 @@
                reg = <0x0 0x12C90000 0x9000>;
                interrupts = <0 183 0>,
                             <0 184 0>;
-               /*
+               qos = <15>;
                clock-names = "aclk";
-               clocks = <&clock GATE_SMMU_XXX>;
-                */
+               clocks = <&clock GATE_SYSMMU_MFCD1_QCH>;
                port-name = "MFC1";
                sysmmu,secure-irq;
                sysmmu,secure_base = <0x12CA0000>;
-               /*
                sysmmu,tlb_property =
-                */
+                       <(SYSMMU_PORT_NO_PREFETCH_READ(0x0)      | SYSMMU_BL8) SYSMMU_NOID>,
+                       <(SYSMMU_PORT_NO_PREFETCH_READWRITE(0x1) | SYSMMU_BL2) SYSMMU_ID_MASK(0x1, 0x1)>;
                #iommu-cells = <0>;
        };
 
@@ -95,16 +88,16 @@
                reg = <0x0 0x12E70000 0x9000>;
                interrupts = <0 168 0>,
                             <0 169 0>;
-               /*
+               qos = <15>;
                clock-names = "aclk";
-               clocks = <&clock GATE_SMMU_XXX>;
-                */
+               clocks = <&clock GATE_SYSMMU_G2D_QCH>;
                port-name = "G2D,MSCL,JPEG";
                sysmmu,secure-irq;
                sysmmu,secure_base = <0x12E80000>;
-               /*
                sysmmu,tlb_property =
-                */
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x0) | SYSMMU_BL16) SYSMMU_NOID>,
+                       <(SYSMMU_PORT_NO_PREFETCH_READ(0x1)         | SYSMMU_BL32) SYSMMU_ID_MASK(0x1, 0x3)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL8)  SYSMMU_ID_MASK(0x2, 0x3)>;
                #iommu-cells = <0>;
        };
 
@@ -113,16 +106,47 @@
                reg = <0x0 0x14550000 0x9000>;
                interrupts = <0 341 0>,
                             <0 342 0>;
-               /*
+               qos = <15>;
                clock-names = "aclk";
-               clocks = <&clock GATE_SMMU_XXX>;
-                */
+               clocks = <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_SMMU>;
                port-name = "CAM";
                sysmmu,secure-irq;
                sysmmu,secure_base = <0x14560000>;
-               /*
                sysmmu,tlb_property =
-                */
+                       /* 0 ~ 17 : PAFSTAT */
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x0)  | SYSMMU_BL1) SYSMMU_NOID>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1)  | SYSMMU_BL1) SYSMMU_ID(0x2)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x0)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x2)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x4)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x6)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x8)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0xA)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0xC)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0xE)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x10)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x12)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x14)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x16)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x18)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x1A)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x1C)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x1E)>,
+                       /* 18 ~ 31 : 3AA */
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x1)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x3)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x5)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x7)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x9)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0xB)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0xD)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0xF)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x11)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x13)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x15)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x17)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x19)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID(0x1B)>;
                #iommu-cells = <0>;
        };
 
@@ -131,16 +155,29 @@
                reg = <0x0 0x14740000 0x9000>;
                interrupts = <0 351 0>,
                             <0 352 0>;
-               /*
+               qos = <15>;
                clock-names = "aclk";
-               clocks = <&clock GATE_SMMU_XXX>;
-                */
+               clocks = <&clock GATE_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0>;
                port-name = "ISP/VRA/GDC";
                sysmmu,secure-irq;
                sysmmu,secure_base = <0x14750000>;
-               /*
                sysmmu,tlb_property =
-                */
+                       /* 0 ~ 7 : ISP */
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x0)  | SYSMMU_BL1) SYSMMU_NOID>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1)  | SYSMMU_BL1) SYSMMU_ID_MASK(0x4, 0xF)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1)  | SYSMMU_BL1) SYSMMU_ID_MASK(0x8, 0xF)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1)  | SYSMMU_BL1) SYSMMU_ID_MASK(0xC, 0xF)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x0, 0xF)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x4, 0xF)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x8, 0xF)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xC, 0xF)>,
+                       /* 8 ~ 9 : VRA */
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1)  | SYSMMU_BL1) SYSMMU_ID_MASK(0x1, 0xF)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1, 0xF)>,
+                       /* 10 ~ 12 : GDC */
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1)  | SYSMMU_BL4)  SYSMMU_ID_MASK(0x2, 0x3)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL32) SYSMMU_ID_MASK(0x2, 0x7)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL32) SYSMMU_ID_MASK(0x6, 0x7)>;
                #iommu-cells = <0>;
        };
 
@@ -149,16 +186,49 @@
                reg = <0x0 0x14770000 0x9000>;
                interrupts = <0 355 0>,
                             <0 356 0>;
-               /*
+               qos = <15>;
                clock-names = "aclk";
-               clocks = <&clock GATE_SMMU_XXX>;
-                */
+               clocks = <&clock GATE_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1>;
                port-name = "MCSC";
                sysmmu,secure-irq;
                sysmmu,secure_base = <0x14780000>;
-               /*
                sysmmu,tlb_property =
-                */
+                       /* 0 ~ 34 : MC_SCALER */
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x0)  | SYSMMU_BL1) SYSMMU_NOID>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1)  | SYSMMU_BL1) SYSMMU_ID_MASK(0x1, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1)  | SYSMMU_BL1) SYSMMU_ID_MASK(0x2, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1)  | SYSMMU_BL1) SYSMMU_ID_MASK(0x3, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1)  | SYSMMU_BL1) SYSMMU_ID_MASK(0x4, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1)  | SYSMMU_BL1) SYSMMU_ID_MASK(0x5, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1)  | SYSMMU_BL1) SYSMMU_ID_MASK(0x6, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1)  | SYSMMU_BL1) SYSMMU_ID_MASK(0x7, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1)  | SYSMMU_BL1) SYSMMU_ID_MASK(0x8, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1)  | SYSMMU_BL1) SYSMMU_ID_MASK(0x9, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x0, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x2, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x3, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x4, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x5, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x6, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x7, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x8, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xF, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x10, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x11, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x12, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x13, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x14, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x15, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x16, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x17, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x18, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x19, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1A, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1F, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x20, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x21, 0x3F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x22, 0x3F)>;
                #iommu-cells = <0>;
        };
 
@@ -167,16 +237,22 @@
                reg = <0x0 0x14820000 0x9000>;
                interrupts = <0 218 0>,
                             <0 217 0>;
-               /*
+               qos = <15>;
                clock-names = "aclk";
-               clocks = <&clock GATE_SMMU_XXX>;
-                */
+               clocks = <&clock GATE_SMMU_DPU_QCH>;
                port-name = "DPU";
                sysmmu,secure-irq;
                sysmmu,secure_base = <0x14830000>;
-               /*
                sysmmu,tlb_property =
-                */
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x0) | SYSMMU_BL1) SYSMMU_NOID>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x8,  0x1F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x9,  0x1F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x10, 0x1F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x0,  0x1F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x14, 0x1F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x15, 0x1F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x16, 0x1F)>,
+                       <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x17, 0x1F)>;
                #iommu-cells = <0>;
        };
 
@@ -184,15 +260,13 @@
                compatible = "samsung,exynos-sysmmu";
                reg = <0x0 0x14920000 0x9000>;
                interrupts = <0 216 0>;
-               /*
+               qos = <15>;
                clock-names = "aclk";
-               clocks = <&clock GATE_SMMU_XXX>;
-                */
+               clocks = <&clock GATE_SMMU_ABOX_QCH>;
                port-name = "ABox";
                sysmmu,no-suspend;
-               /*
                sysmmu,tlb_property =
-                */
+                       <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL1) SYSMMU_NOID>;
                #iommu-cells = <0>;
        };
 };