ARM: dts: dra7: Add updated operating-points-v2 table for cpu

After the ti-cpufreq driver has been added, we can now drop the
operating-points table present in dra7.dtsi for the cpu and add an
operating-points-v2 table with all OPPs available for all silicon
revisions. Also add necessary data for use by ti-cpufreq to selectively
enable the appropriate OPPs at runtime as part of the operating-points
table.

As we now need to define voltage ranges for each OPP, we define the
minimum and maximum voltage to match the ranges possible for AVS class0
voltage as defined by the DRA7/AM57 Data Manual, with the exception of
using a range for OPP_OD based on historical data to ensure that SoCs
from older lots still continue to boot, even though more optimal voltages
are now the standard. Once an AVS Class0 driver is in place it will be
possible for these OPP voltages to be adjusted to any voltage within the
provided range.

Information from SPRS953, Revised December 2015.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
eviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 2c9e56f4aac53aa74c206b2cbb3622965d7ab792..e9dc314b0dcf53ec1081b6ce08cdb14e5dd518cc 100644 (file)
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -81,11 +81,7 @@
                        compatible = "arm,cortex-a15";
                        reg = <0>;
 
-                       operating-points = <
-                               /* kHz    uV */
-                               1000000 1060000
-                               1176000 1160000
-                               >;
+                       operating-points-v2 = <&cpu0_opp_table>;
 
                        clocks = <&dpll_mpu_ck>;
                        clock-names = "cpu";
@@ -99,6 +95,24 @@
                };
        };
 
+       cpu0_opp_table: opp-table {
+               compatible = "operating-points-v2-ti-cpu";
+               syscon = <&scm_wkup>;
+
+               opp_nom@1000000000 {
+                       opp-hz = /bits/ 64 <1000000000>;
+                       opp-microvolt = <1060000 850000 1150000>;
+                       opp-supported-hw = <0xFF 0x01>;
+                       opp-suspend;
+               };
+
+               opp_od@1176000000 {
+                       opp-hz = /bits/ 64 <1176000000>;
+                       opp-microvolt = <1160000 885000 1160000>;
+                       opp-supported-hw = <0xFF 0x02>;
+               };
+       };
+
        /*
         * The soc node represents the soc top level view. It is used for IPs
         * that are not memory mapped in the MPU view or for the MPU itself.

diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 0a78347e6615651b16bf0b50bff32c50f55103b8..24e6746c5b262602ac70f4935d23842ba8454fbe 100644 (file)
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -17,6 +17,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a15";
                        reg = <1>;
+                       operating-points-v2 = <&cpu0_opp_table>;
                };
        };
 
@@ -79,6 +80,10 @@
        };
 };
 
+&cpu0_opp_table {
+       opp-shared;
+};
+
 &dss {
        reg = <0x58000000 0x80>,
              <0x58004054 0x4>,