CPUs implementing LPAE have atomic ldrd/strd instructions, meaning that
userspace software can avoid having to use the exclusive variants of
these instructions if they wish.
This patch advertises the atomicity of these instructions via the
hwcaps, so userspace can detect this CPU feature.
Reported-by: Vladimir Danushevsky <vladimir.danushevsky@oracle.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
#define HWCAP_IDIVT (1 << 18)
#define HWCAP_VFPD32 (1 << 19) /* set if VFP has 32 regs (not 16) */
#define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT)
-
+#define HWCAP_LPAE (1 << 20)
#endif /* _UAPI__ASMARM_HWCAP_H */
static void __init cpuid_init_hwcaps(void)
{
- unsigned int divide_instrs;
+ unsigned int divide_instrs, vmsa;
if (cpu_architecture() < CPU_ARCH_ARMv7)
return;
case 1:
elf_hwcap |= HWCAP_IDIVT;
}
+
+ /* LPAE implies atomic ldrd/strd instructions */
+ vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0;
+ if (vmsa >= 5)
+ elf_hwcap |= HWCAP_LPAE;
}
static void __init feat_v6_fixup(void)
"vfpv4",
"idiva",
"idivt",
+ "lpae",
NULL
};