coresight-etm4x: Read only access to the main management registers

Having access to the ETMv4 management registers is very useful as they
give meaningful information on how the IP block has been configured at
synthesis time.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
index 648f28ded2269b8829ed4f7dc3029141fc7bb24d..bde788dfd3f72c3205e3d8d38abe7ee26e33803b 100644 (file)
--- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
+++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
@@ -281,3 +281,80 @@ KernelVersion:     4.01
 Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:   (RW) Mask for all 8 virtual machine ID comparator value
                registers (if implemented).
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcoslsr
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (R) Print the content of the OS Lock Status Register (0x304).
+               The value it taken directly  from the HW.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdcr
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (R) Print the content of the Power Down Control Register
+               (0x310).  The value is taken directly from the HW.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdsr
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (R) Print the content of the Power Down Status Register
+               (0x314).  The value is taken directly from the HW.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trclsr
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (R) Print the content of the SW Lock Status Register
+               (0xFB4).  The value is taken directly from the HW.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcauthstatus
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (R) Print the content of the Authentication Status Register
+               (0xFB8).  The value is taken directly from the HW.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevid
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (R) Print the content of the Device ID Register
+               (0xFC8).  The value is taken directly from the HW.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevtype
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (R) Print the content of the Device Type Register
+               (0xFCC).  The value is taken directly from the HW.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr0
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (R) Print the content of the Peripheral ID0 Register
+               (0xFE0).  The value is taken directly from the HW.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr1
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (R) Print the content of the Peripheral ID1 Register
+               (0xFE4).  The value is taken directly from the HW.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr2
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (R) Print the content of the Peripheral ID2 Register
+               (0xFE8).  The value is taken directly from the HW.
+
+What:          /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr3
+Date:          April 2015
+KernelVersion: 4.01
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (R) Print the content of the Peripheral ID3 Register
+               (0xFEC).  The value is taken directly from the HW.

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 02ee6fc97ddfa725e84489fa36429c6348998fbb..0568e4413411bb14053d832f544c25ba31c102a2 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -2200,7 +2200,58 @@ static struct attribute *coresight_etmv4_attrs[] = {
        &dev_attr_cpu.attr,
        NULL,
 };
-ATTRIBUTE_GROUPS(coresight_etmv4);
+
+#define coresight_simple_func(name, offset)                            \
+static ssize_t name##_show(struct device *_dev,                                \
+                          struct device_attribute *attr, char *buf)    \
+{                                                                      \
+       struct etmv4_drvdata *drvdata = dev_get_drvdata(_dev->parent);  \
+       return scnprintf(buf, PAGE_SIZE, "0x%x\n",                      \
+                        readl_relaxed(drvdata->base + offset));        \
+}                                                                      \
+DEVICE_ATTR_RO(name)
+
+coresight_simple_func(trcoslsr, TRCOSLSR);
+coresight_simple_func(trcpdcr, TRCPDCR);
+coresight_simple_func(trcpdsr, TRCPDSR);
+coresight_simple_func(trclsr, TRCLSR);
+coresight_simple_func(trcauthstatus, TRCAUTHSTATUS);
+coresight_simple_func(trcdevid, TRCDEVID);
+coresight_simple_func(trcdevtype, TRCDEVTYPE);
+coresight_simple_func(trcpidr0, TRCPIDR0);
+coresight_simple_func(trcpidr1, TRCPIDR1);
+coresight_simple_func(trcpidr2, TRCPIDR2);
+coresight_simple_func(trcpidr3, TRCPIDR3);
+
+static struct attribute *coresight_etmv4_mgmt_attrs[] = {
+       &dev_attr_trcoslsr.attr,
+       &dev_attr_trcpdcr.attr,
+       &dev_attr_trcpdsr.attr,
+       &dev_attr_trclsr.attr,
+       &dev_attr_trcauthstatus.attr,
+       &dev_attr_trcdevid.attr,
+       &dev_attr_trcdevtype.attr,
+       &dev_attr_trcpidr0.attr,
+       &dev_attr_trcpidr1.attr,
+       &dev_attr_trcpidr2.attr,
+       &dev_attr_trcpidr3.attr,
+       NULL,
+};
+
+static const struct attribute_group coresight_etmv4_group = {
+       .attrs = coresight_etmv4_attrs,
+};
+
+static const struct attribute_group coresight_etmv4_mgmt_group = {
+       .attrs = coresight_etmv4_mgmt_attrs,
+       .name = "mgmt",
+};
+
+static const struct attribute_group *coresight_etmv4_groups[] = {
+       &coresight_etmv4_group,
+       &coresight_etmv4_mgmt_group,
+       NULL,
+};
 
 static void etm4_init_arch_data(void *info)
 {