};
/*iso7816*/
-static const unsigned int iso7816_clk_pins[] = { GPIOZ_6 };
-static const unsigned int iso7816_data_pins[] = { GPIOZ_7 };
+static const unsigned int iso7816_clk_dv_pins[] = { GPIODV_22 };
+static const unsigned int iso7816_data_dv_pins[] = { GPIODV_23 };
static struct meson_pmx_group meson_gxl_periphs_groups[] = {
GPIO_GROUP(GPIOZ_0),
GROUP(tsin_fail_b_z4, 3, 15), /*z4*/
GROUP(dvp_d2_9, 3, 11), /*z4*/
GROUP(i2sout_ch23_z5, 3, 26), /*z5*/
- GROUP(iso7816_clk, 4, 9), /*z6*/
GROUP(i2sout_ch45_z6, 3, 25), /*z6*/
GROUP(i2sout_ch67_z7, 3, 24), /*z7*/
GROUP(spi_sclk_0, 4, 4), /*z11*/
GROUP(i2c_scl_c_dv19, 1, 16), /*dv19*/
GROUP(pwm_b, 2, 11), /*dv29*/
GROUP(pwm_d, 2, 12), /*dv28*/
+ GROUP(iso7816_clk_dv, 2, 18), /*dv22*/
+ GROUP(iso7816_data_dv, 2, 17), /*dv23*/
/* Bank BOOT */
GROUP(emmc_nand_d07, 7, 31),
"dmic_in_z8", "dmic_clk_z9",
};
+static const char * const iso7816_groups[] = {
+ "iso7816_clk_dv", "iso7816_data_dv",
+};
+
+
static struct meson_pmx_func meson_gxl_periphs_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(emmc),
FUNCTION(uart_a),
FUNCTION(uart_b),
FUNCTION(uart_c),
+ FUNCTION(iso7816),
FUNCTION(eth),
FUNCTION(jtag),
FUNCTION(pwm_a),
#define __MACH_MESON8_REG_ADDR_H_
#include <linux/amlogic/iomap.h>
#define CBUS_REG_ADDR(_r) aml_read_cbus(_r)
-#define SMARTCARD_REG0 0x2110
+#define SMARTCARD_REG_BASE smc_get_reg_base()
+#define SMARTCARD_REG0 (SMARTCARD_REG_BASE + 0x0)
#define P_SMARTCARD_REG0 CBUS_REG_ADDR(SMARTCARD_REG0)
-#define SMARTCARD_REG1 0x2111
+#define SMARTCARD_REG1 (SMARTCARD_REG_BASE + 0x1)
#define P_SMARTCARD_REG1 CBUS_REG_ADDR(SMARTCARD_REG1)
-#define SMARTCARD_REG2 0x2112
+#define SMARTCARD_REG2 (SMARTCARD_REG_BASE + 0x2)
#define P_SMARTCARD_REG2 CBUS_REG_ADDR(SMARTCARD_REG2)
-#define SMARTCARD_STATUS 0x2113
+#define SMARTCARD_STATUS (SMARTCARD_REG_BASE + 0x3)
#define P_SMARTCARD_STATUS CBUS_REG_ADDR(SMARTCARD_STATUS)
-#define SMARTCARD_INTR 0x2114
+#define SMARTCARD_INTR (SMARTCARD_REG_BASE + 0x4)
#define P_SMARTCARD_INTR CBUS_REG_ADDR(SMARTCARD_INTR)
-#define SMARTCARD_REG5 0x2115
+#define SMARTCARD_REG5 (SMARTCARD_REG_BASE + 0x5)
#define P_SMARTCARD_REG5 CBUS_REG_ADDR(SMARTCARD_REG5)
-#define SMARTCARD_REG6 0x2116
+#define SMARTCARD_REG6 (SMARTCARD_REG_BASE + 0x6)
#define P_SMARTCARD_REG6 CBUS_REG_ADDR(SMARTCARD_REG6)
-#define SMARTCARD_FIFO 0x2117
+#define SMARTCARD_FIFO (SMARTCARD_REG_BASE + 0x7)
#define P_SMARTCARD_FIFO CBUS_REG_ADDR(SMARTCARD_FIFO)
-#define SMARTCARD_REG8 0x2118
+#define SMARTCARD_REG8 (SMARTCARD_REG_BASE + 0x8)
#define P_SMARTCARD_REG8 CBUS_REG_ADDR(SMARTCARD_REG8)
#endif
static struct file *debug_filp;
static loff_t debug_file_pos;
static int smc_debug;
+#ifdef MEM_DEBUG
static char *dbuf;
static int dread, dwrite;
static int dcnt;
-static struct reset_control *aml_smartcard_reset_ctrl;
+#endif
+/*no used reset ctl,need use clk in 4.9 kernel*/
+static struct clk *aml_smartcard_clk;
+
#define REG_READ 0
#define REG_WRITE 1
void operate_reg(unsigned int reg, int read_write, unsigned int *value)
set_fs(old_fs);
}
+
+#ifdef MEM_DEBUG
static void open_debug(void)
{
debug_filp = filp_open(DEBUG_FILE_NAME, O_WRONLY, 0);
return sprintf(buf, "[%5lu.%06lu] ",
(unsigned long)ts, rem_nsec / 1000);
}
+#endif
#ifdef CONFIG_OF
static const struct of_device_id smc_dt_match[] = {
static int smc_major;
static struct smc_dev smc_dev[SMC_DEV_COUNT];
static int ENA_GPIO_PULL = 1;
+static int DIV_SMC = 3;
#ifdef SW_INVERT
static const unsigned char inv_table[256] = {
return count;
}
+static ssize_t show_div_smc(struct class *class,
+ struct class_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "div -> %d\n", DIV_SMC);
+}
+
+static ssize_t store_div_smc(struct class *class,
+ struct class_attribute *attr,
+ const char *buf,
+ size_t count)
+{
+ int div = 0;
+
+ if (kstrtoint(buf, 0, &div))
+ return -EINVAL;
+
+ if (div)
+ DIV_SMC = div;
+
+ pr_dbg("div -> %d\n", DIV_SMC);
+ return count;
+}
+
#ifdef MEM_DEBUG
static ssize_t show_debug(struct class *class,
struct class_attribute *attr,
__ATTR(smc_gpio_pull, 0644, show_gpio_pull, set_gpio_pull),
__ATTR(ctrl_5v3v, 0644, show_5v3v, store_5v3v),
__ATTR(freq, 0644, show_freq, store_freq),
+ __ATTR(div_smc, 0644, show_div_smc, store_div_smc),
#ifdef MEM_DEBUG
__ATTR(debug, 0644, show_debug, store_debug),
#endif
.class_attrs = smc_class_attrs,
};
-static unsigned long get_clk(char *name)
-{
- struct clk *clk = NULL;
- clk = clk_get_sys(name, NULL);
- if (clk)
- return clk_get_rate(clk);
- return 0;
-}
-static unsigned long get_module_clk(int sel)
+long smc_get_reg_base(void)
{
-#ifdef CONFIG_ARCH_ARC700
- return get_mpeg_clk();
-#else
+ int newbase = 0;
- unsigned long clk = 0;
-#ifdef CONFIG_ARCH_MESON6/*M6*/
- /*sel = [0:clk81, 1:ddr-pll, 2:fclk-div5, 3:XTAL]*/
- switch (sel) {
- case 0:
- clk = get_clk("clk81");
- break;
- case 1:
- clk = get_clk("pll_ddr");
- break;
- case 2:
- clk = get_clk("fixed")/5;
- break;
- case 3:
- clk = get_clk("xtal");
- break;
- }
-#else
- /*
- * sel = [0:fclk-div2/fclk-div4(M8 and further),
- * 1:fclk-div3, 2:fclk-div5, 3:XTAL]
- */
- switch (sel) {
-#if defined(MESON_CPU_TYPE_MESON8) && (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8)
- case 0:
- clk = get_clk("pll_fixed") / 4;
- break;
-#else/*M6TV/TVD/TVLITE*/
- case 0:
- clk = 1000000000;
- break;
- /*
- * case 0: clk = get_clk("fixed")/2;
- * break;
- */
-#endif
- case 1:
- clk = get_clk("pll_fixed") / 3;
- break;
- case 2:
- clk = get_clk("pll_fixed") / 5;
- break;
- case 3:
- clk = get_clk("xtal");
- break;
+ if (get_cpu_type() > MESON_CPU_MAJOR_ID_TXL &&
+ get_cpu_type() != MESON_CPU_MAJOR_ID_GXLX) {
+ newbase = 1;
}
-#endif /*M6*/
-
- if (!clk)
- pr_error("fail: unknown clk source");
-
- return clk;
-
-#endif
+ return (newbase) ? 0x9400 : 0x2110;
}
#ifndef CONFIG_OF
* SMC_ANSWER_TO_RST *reg1;
* SMC_INTERRUPT_Reg *reg_int;
*/
- unsigned int sys_clk_rate = get_module_clk(clock_source);
- unsigned long freq_cpu =
- sys_clk_rate / 1000 * 22; /**10 adjust freq temporarily*/
+ unsigned long freq_cpu = clk_get_rate(aml_smartcard_clk)/1000*DIV_SMC;
pr_error("hw set param\n");
pr_error("xmit_par:%d\n", smc->param.xmit_parity);
pr_error("xmit_rep:%d\n", smc->param.xmit_repeat_dis);
pr_error("xmit_try:%d\n", smc->param.xmit_retries);
+ pr_error("clk_tcnt:%d freq_cpu:%ld\n", reg2->clk_tcnt, freq_cpu);
v = SMC_READ_REG(REG5);
reg5 = (struct SMCCARD_HW_Reg5 *)&v;
struct SMCCARD_HW_Reg5 *reg5;
struct SMCCARD_HW_Reg6 *reg6;
- unsigned int sys_clk_rate = get_module_clk(clock_source);
-
- unsigned long freq_cpu = sys_clk_rate
- / 1000 * 22; /**10 adjust freq temporarily*/
+ unsigned long freq_cpu = clk_get_rate(aml_smartcard_clk)/1000*DIV_SMC;
pr_error("SMC CLK SOURCE - %luKHz\n", freq_cpu);
pr_error("xmit_par:%d\n", smc->param.xmit_parity);
pr_error("xmit_rep:%d\n", smc->param.xmit_repeat_dis);
pr_error("xmit_try:%d\n", smc->param.xmit_retries);
+ pr_error("clk_tcnt:%d freq_cpu:%ld\n", reg2->clk_tcnt, freq_cpu);
v = SMC_READ_REG(INTR);
reg_int = (struct SMC_INTERRUPT_Reg *)&v;
} else {
if (smc->use_enable_pin)
_gpio_out(smc->enable_pin,
- !smc->enable_level,
+ smc->enable_level,
SMC_ENABLE_PIN_NAME);
}
if (ENA_GPIO_PULL > 0) {
}
if (smc->use_enable_pin)
_gpio_free(smc->enable_pin, SMC_ENABLE_PIN_NAME);
- reset_control_assert(aml_smartcard_reset_ctrl);
+ clk_disable_unprepare(aml_smartcard_clk);
#if 0
if (smc->pin_clk_pin != -1)
_gpio_free(smc->pin_clk_pin, SMC_CLK_PIN_NAME);
} else if (input_output == INPUT) {
*gpiod = gpiod_get(&smc->pdev->dev, str, GPIOD_IN);
ret = gpiod_direction_input(*gpiod);
- //ret |= gpiod_set_pullup(*gpiod, 1);
+ ret |= gpiod_set_pull(*gpiod, GPIOD_PULL_UP);
} else
pr_dbg("SMC Request gpio direction invalid\n");
u32 value;
char buf[32];
const char *dts_str;
+ struct resource *res;
#endif
#if defined(MESON_CPU_TYPE_MESON8) && (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8)
pr_error("%s: %d\n", buf, smc->enable_level);
if (smc->enable_pin != NULL) {
_gpio_out(smc->enable_pin,
- !smc->enable_level,
+ smc->enable_level,
SMC_ENABLE_PIN_NAME);
pr_error("enable_pin: -->(%d)\n",
(!smc->enable_level)?1:0);
smc->irq_num = smc0_irq;
if (smc->irq_num == -1) {
snprintf(buf, sizeof(buf), "smc%d_irq", id);
-#ifdef CONFIG_OF
+#if 0
ret = of_property_read_u32(smc->pdev->dev.of_node, buf, &value);
if (!ret) {
smc->irq_num = value;
}
#endif
-#if 0
+#if 1
smc->enable_5v3v_level = 0;
if (1) {
snprintf(buf, sizeof(buf), "smc%d_5v3v_level", id);
if (!ret) {
smc->enable_5v3v_level = value;
pr_error("%s: %d\n", buf, smc->enable_5v3v_level);
- if (smc->enable_5v3v_pin != -1) {
+ if (smc->enable_5v3v_pin != NULL) {
_gpio_out(smc->enable_5v3v_pin,
smc->enable_5v3v_level,
SMC_ENABLE_5V3V_PIN_NAME);
#else
smc->irq_num = request_irq(smc->irq_num,
(irq_handler_t)smc_irq_handler,
- IRQF_SHARED, "smc", smc);
+ IRQF_SHARED|IRQF_TRIGGER_RISING, "smc", smc);
if (smc->irq_num < 0) {
pr_error("request irq error!\n");
smc_dev_deinit(smc);
break;
}
}
- aml_smartcard_reset_ctrl =
- devm_reset_control_get(&pdev->dev, "smartcard");
- reset_control_deassert(aml_smartcard_reset_ctrl);
+ aml_smartcard_clk =
+ devm_clk_get(&pdev->dev, "smartcard");
+ if (IS_ERR_OR_NULL(aml_smartcard_clk)) {
+ dev_err(&pdev->dev, "get smartcard clk fail\n");
+ return -1;
+ }
+ clk_prepare_enable(aml_smartcard_clk);
if (smc) {
smc->init = 1;
smc->pdev = pdev;