drm/i915: Set the LVDS_BORDER when using LVDS scaling mode

According to the spec the LVDS_BORDER_ENABLE bit decides whether the border
data should be included in the active display and data sent to the panel.
Border should be used when in VGA centered (un-scaled) mode or when scaling
a 4:3 source image to a wide screen panel (typical 16:9).

So when the LVDS scaling is used, decide whether the LVDS_BORDER should be
enabled or not according to the current scaling mode.

At the same time fix the typo error in LVDS center scaling mode.

https://bugs.freedesktop.org/show_bug.cgi?id=23789

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
tested-by: Zhao Jian <jian.zhao@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0094f185e17dff8f49362c6f6d82e58a18ba1ce3..17be01e351b3fa9d8713988152495feda239d461 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -492,6 +492,8 @@ typedef struct drm_i915_private {
                struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
        } mm;
        struct sdvo_device_mapping sdvo_mappings[2];
+       /* indicate whether the LVDS_BORDER should be enabled or not */
+       unsigned int lvds_border_bits;
 
        /* Reclocking support */
        bool render_reclock_avail;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0466ddbeba3297e9d774665be2840d9098a29a82..5f9272459b71445fd8fb3d066401bbd7a468ca9b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -968,6 +968,8 @@
 #define   LVDS_PORT_EN                 (1 << 31)
 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
 #define   LVDS_PIPEB_SELECT            (1 << 30)
+/* Enable border for unscaled (or aspect-scaled) display */
+#define   LVDS_BORDER_ENABLE           (1 << 15)
 /*
  * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
  * pixel.

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3c14240cc0028d32cada1af63a069e78776ea306..9efe11761be37ddd70b0a394277be2ec3f3a27b8 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2936,6 +2936,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 
                lvds = I915_READ(lvds_reg);
                lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
+               /* set the corresponsding LVDS_BORDER bit */
+               lvds |= dev_priv->lvds_border_bits;
                /* Set the B0-B3 data pairs corresponding to whether we're going to
                 * set the DPLLs for dual-channel mode or not.
                 */

diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 98ae3d73577ee473ed927065b2c0d6e540c33b36..089f18c66ddbab5a5558f3c5485f377852618072 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -380,7 +380,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
                                adjusted_mode->crtc_vblank_start + vsync_pos;
                /* keep the vsync width constant */
                adjusted_mode->crtc_vsync_end =
-                               adjusted_mode->crtc_vblank_start + vsync_width;
+                               adjusted_mode->crtc_vsync_start + vsync_width;
                border = 1;
                break;
        case DRM_MODE_SCALE_ASPECT:
@@ -525,6 +525,14 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
 out:
        lvds_priv->pfit_control = pfit_control;
        lvds_priv->pfit_pgm_ratios = pfit_pgm_ratios;
+       /*
+        * When there exists the border, it means that the LVDS_BORDR
+        * should be enabled.
+        */
+       if (border)
+               dev_priv->lvds_border_bits |= LVDS_BORDER_ENABLE;
+       else
+               dev_priv->lvds_border_bits &= ~(LVDS_BORDER_ENABLE);
        /*
         * XXX: It would be nice to support lower refresh rates on the
         * panels to reduce power consumption, and perhaps match the