if ( NULL != p )
{
memcpy(p, dev, sizeof(dbdev_tab_t));
- p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id);
+ p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id);
ret = p->dev_id;
new_id++;
#if 0
spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
if (!(stp->dev_flags & DEV_FLAGS_INUSE) ||
(stp->dev_flags & DEV_FLAGS_ANYUSE)) {
- /* Got source */
+ /* Got source */
stp->dev_flags |= DEV_FLAGS_INUSE;
if (!(dtp->dev_flags & DEV_FLAGS_INUSE) ||
(dtp->dev_flags & DEV_FLAGS_ANYUSE)) {
return -EINVAL;
#else
if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
- return -EINVAL;
+ return -EINVAL;
#endif
for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) {
static struct platform_device smc91x_device = {
.name = "smc91x",
- .id = -1,
+ .id = -1,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
&au1xxx_mmc_device,
#endif
#ifdef CONFIG_MIPS_DB1200
- &smc91x_device,
+ &smc91x_device,
#endif
};
else {
/* Clear to obtain best system bus performance */
clear_c0_config(1<<19); /* Clear Config[OD] */
- }
+ }
argptr = prom_getcmdline();
: "hi", "lo", GCC_REG_ACCUM);
/*
- * Due to possible jiffies inconsistencies, we need to check
+ * Due to possible jiffies inconsistencies, we need to check
* the result so that we'll get a timer that is monotonic.
*/
if (res >= USECS_PER_JIFFY)
*/
for (memory_page = (unsigned char *)CKSEG1 + CHUNK_SIZE;
mem_err == 0 && memory_page < (unsigned char *)CKSEG1 + 0x1e00000;
- memory_page += CHUNK_SIZE) {
+ memory_page += CHUNK_SIZE) {
dummy = *memory_page;
}
memcpy((void *)(CKSEG0 + 0x80), &old_handler, 0x80);
and t2,s1
sh t2,JAZZ_IO_IRQ_ENABLE
- nor s1,zero,s1
+ nor s1,zero,s1
jal do_IRQ
- /*
- * Reenable interrupt
- */
+ /*
+ * Reenable interrupt
+ */
lhu t2,JAZZ_IO_IRQ_ENABLE
- or t2,s1
+ or t2,s1
sh t2,JAZZ_IO_IRQ_ENABLE
- j ret_from_irq
+ j ret_from_irq
/*
* "Jump extender" to reach spurious_interrupt
* for documentation. Commented out because it shares
* it's c0_prid id number with the TX3900.
*/
- c->cputype = CPU_R4650;
+ c->cputype = CPU_R4650;
c->isa_level = MIPS_CPU_ISA_III;
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
c->tlbsize = 48;
case PRID_IMP_AU1_REV2:
switch ((c->processor_id >> 24) & 0xff) {
case 0:
- c->cputype = CPU_AU1000;
+ c->cputype = CPU_AU1000;
break;
case 1:
c->cputype = CPU_AU1500;
break;
case PRID_COMP_PHILIPS:
cpu_probe_philips(c);
- break;
+ break;
default:
c->cputype = CPU_UNKNOWN;
}
*/
.align 5
NESTED(trap_low, GDB_FR_SIZE, sp)
- .set noat
+ .set noat
.set noreorder
mfc0 k0, CP0_STATUS
sp = regs->regs[29];
/*
- * FPU emulator may have it's own trampoline active just
- * above the user stack, 16-bytes before the next lowest
- * 16 byte boundary. Try to avoid trashing it.
- */
- sp -= 32;
+ * FPU emulator may have it's own trampoline active just
+ * above the user stack, 16-bytes before the next lowest
+ * 16 byte boundary. Try to avoid trashing it.
+ */
+ sp -= 32;
/* This is the X/Open sanctioned signal stack switching. */
if ((ka->sa.sa_flags & SA_ONSTACK) && (sas_ss_flags (sp) == 0))
sp = regs->regs[29];
/*
- * FPU emulator may have it's own trampoline active just
- * above the user stack, 16-bytes before the next lowest
- * 16 byte boundary. Try to avoid trashing it.
- */
- sp -= 32;
+ * FPU emulator may have it's own trampoline active just
+ * above the user stack, 16-bytes before the next lowest
+ * 16 byte boundary. Try to avoid trashing it.
+ */
+ sp -= 32;
/* This is the X/Open sanctioned signal stack switching. */
if ((ka->sa.sa_flags & SA_ONSTACK) && (sas_ss_flags (sp) == 0))
}
#endif
/*
- * Unimplemented operation exception. If we've got the full
+ * Unimplemented operation exception. If we've got the full
* software emulator on-board, let's use it...
*
* Force FPU to dump state into task/thread context. We're
_image_start = ADDR(.data);
_image_size = SIZEOF(.data);
- .other : {
- *(.*)
+ .other :
+ {
+ *(.*)
}
}
and s0, s1
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
- .set mips32
+ .set mips32
clz a0, s0
.set mips0
negu a0
andi a0, s0, CAUSEF_IP3 # delay slot, check hw1 interrupt
#else
beq a0, zero, 1f # delay slot, check hw3 interrupt
- andi a0, s0, CAUSEF_IP5
+ andi a0, s0, CAUSEF_IP5
#endif
/* Wheee, combined hardware level zero interrupt. */
and s0, s1
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
- .set mips32
+ .set mips32
clz a0, s0
.set mips0
negu a0
#ifdef CONFIG_MIPS_MT_SMTC
void mipsmt_prepare_cpus(int c);
/*
- * As noted above, we can assume a single CPU for now
+ * As noted above, we can assume a single CPU for now
* but it may be multithreaded.
*/
"sb\t$0, 0x014(%0)\n\t"
"sb\t$0, 0x018(%0)\n\t"
"sb\t$0, 0x01c(%0)\n\t"
- "sb\t$0, 0x020(%0)\n\t"
+ "sb\t$0, 0x020(%0)\n\t"
"sb\t$0, 0x024(%0)\n\t"
"sb\t$0, 0x028(%0)\n\t"
"sb\t$0, 0x02c(%0)\n\t"
"sb\t$0, 0x054(%0)\n\t"
"sb\t$0, 0x058(%0)\n\t"
"sb\t$0, 0x05c(%0)\n\t"
- "sb\t$0, 0x060(%0)\n\t"
+ "sb\t$0, 0x060(%0)\n\t"
"sb\t$0, 0x064(%0)\n\t"
"sb\t$0, 0x068(%0)\n\t"
"sb\t$0, 0x06c(%0)\n\t"
"sb\t$0, 0x004(%0)\n\t"
"sb\t$0, 0x008(%0)\n\t"
"sb\t$0, 0x00c(%0)\n\t"
- "sb\t$0, 0x010(%0)\n\t"
+ "sb\t$0, 0x010(%0)\n\t"
"sb\t$0, 0x014(%0)\n\t"
"sb\t$0, 0x018(%0)\n\t"
"sb\t$0, 0x01c(%0)\n\t"
- "sb\t$0, 0x020(%0)\n\t"
+ "sb\t$0, 0x020(%0)\n\t"
"sb\t$0, 0x024(%0)\n\t"
"sb\t$0, 0x028(%0)\n\t"
"sb\t$0, 0x02c(%0)\n\t"
- "sb\t$0, 0x030(%0)\n\t"
+ "sb\t$0, 0x030(%0)\n\t"
"sb\t$0, 0x034(%0)\n\t"
"sb\t$0, 0x038(%0)\n\t"
"sb\t$0, 0x03c(%0)\n\t"
- "sb\t$0, 0x040(%0)\n\t"
+ "sb\t$0, 0x040(%0)\n\t"
"sb\t$0, 0x044(%0)\n\t"
"sb\t$0, 0x048(%0)\n\t"
"sb\t$0, 0x04c(%0)\n\t"
- "sb\t$0, 0x050(%0)\n\t"
+ "sb\t$0, 0x050(%0)\n\t"
"sb\t$0, 0x054(%0)\n\t"
"sb\t$0, 0x058(%0)\n\t"
"sb\t$0, 0x05c(%0)\n\t"
- "sb\t$0, 0x060(%0)\n\t"
+ "sb\t$0, 0x060(%0)\n\t"
"sb\t$0, 0x064(%0)\n\t"
"sb\t$0, 0x068(%0)\n\t"
"sb\t$0, 0x06c(%0)\n\t"
- "sb\t$0, 0x070(%0)\n\t"
+ "sb\t$0, 0x070(%0)\n\t"
"sb\t$0, 0x074(%0)\n\t"
"sb\t$0, 0x078(%0)\n\t"
"sb\t$0, 0x07c(%0)\n\t"
#else
void *nvram = (void*) 0xfc807000;
#endif
- /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
+ /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
writeb(0x84, nvram + 0xff7);
/* wait for the watchdog to go off */
unsigned int tbControl;
tbControl =
0 << 26 | /* post trigger delay 0 */
- 0x2 << 16 | /* sequential trace mode */
+ 0x2 << 16 | /* sequential trace mode */
// 0x0 << 16 | /* non-sequential trace mode */
// 0xf << 4 | /* watchpoints disabled */
2 << 2 | /* armed */
/* base address of timekeeper portion of part */
void *nvram = (void *) 0xfc807000L;
- /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
+ /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
writeb(0x84, nvram + 0xff7);
/* wait for the watchdog to go off */
0xfc807000;
#endif
- /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
+ /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
writeb(0x84, nvram + 0xff7);
/* wait for the watchdog to go off */
/*
* we have to open the bridges' windows down to 0 because otherwise
- * we cannot access ISA south bridge I/O registers that get mapped from
+ * we cannot access ISA south bridge I/O registers that get mapped from
* 0. for example, 8259 PIC would be unaccessible without that
*/
if(dev->vendor == PCI_VENDOR_ID_INTEL && dev->device == PCI_DEVICE_ID_INTEL_S21152BB) {
static int prefix##_##rw##_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 star val) \
{ \
if (size == 1) \
- return rw##_config_byte(pciswap, bus, devfn, where, (u8 star)val); \
+ return rw##_config_byte(pciswap, bus, devfn, where, (u8 star)val); \
else if (size == 2) \
- return rw##_config_word(pciswap, bus, devfn, where, (u16 star)val); \
+ return rw##_config_word(pciswap, bus, devfn, where, (u16 star)val); \
/* Size must be 4 */ \
return rw##_config_dword(pciswap, bus, devfn, where, val); \
}
};
struct resource tx4938_pcic1_pci_io_resource = {
- .name = "PCI1 IO",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_IO
+ .name = "PCI1 IO",
+ .start = 0,
+ .end = 0,
+ .flags = IORESOURCE_IO
};
struct resource tx4938_pcic1_pci_mem_resource = {
- .name = "PCI1 mem",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_MEM
+ .name = "PCI1 mem",
+ .start = 0,
+ .end = 0,
+ .flags = IORESOURCE_MEM
};
static int mkaddr(int bus, int dev_fn, int where, int *flagsp)
if (bus->number == 0) {
devno = PCI_SLOT(devfn);
- if (bcm1480_bus_status & PCI_DEVICE_MODE)
+ if (bcm1480_bus_status & PCI_DEVICE_MODE)
return 0;
else
return 1;
if (bus->number == 0) {
devno = PCI_SLOT(devfn);
- if (bcm1480ht_bus_status & PCI_DEVICE_MODE)
+ if (bcm1480ht_bus_status & PCI_DEVICE_MODE)
return 0;
}
return 1;
bridge = (bridge_t *) RAW_NODE_SWIN_BASE(nasid, widget_id);
/*
- * Clear all pending interrupts.
- */
+ * Clear all pending interrupts.
+ */
bridge->b_int_rst_stat = BRIDGE_IRR_ALL_CLR;
/*
- * Until otherwise set up, assume all interrupts are from slot 0
- */
+ * Until otherwise set up, assume all interrupts are from slot 0
+ */
bridge->b_int_device = 0x0;
/*
- * swap pio's to pci mem and io space (big windows)
- */
+ * swap pio's to pci mem and io space (big windows)
+ */
bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP |
BRIDGE_CTRL_MEM_SWAP;
if (gic_int_line == (PNX8550_INT_GPIO0 - PNX8550_INT_GIC_MIN)) {
/* PCI INT through gpio 8, which is setup in
* pnx8550_setup.c and routed to GPIO
- * Interrupt Level 0 (GPIO Connection 58).
+ * Interrupt Level 0 (GPIO Connection 58).
* Set it active low. */
PNX8550_GIC_REQ(gic_int_line) = 0x1E020000;
struct page *end, *p;
/*
- * This will free up the bootmem, ie, slot 0 memory.
- */
+ * This will free up the bootmem, ie, slot 0 memory.
+ */
totalram_pages += free_all_bootmem_node(NODE_DATA(node));
/*
board_timer_setup = ip32_timer_setup;
#ifdef CONFIG_SERIAL_8250
- {
+ {
static struct uart_port o2_serial[2];
memset(o2_serial, 0, sizeof(o2_serial));
if ((read_c0_prid() & 0xff) == PRID_REV_TX4927) {
mips_machtype = MACH_TOSHIBA_RBTX4927;
- toshiba_name = "TX4927";
+ toshiba_name = "TX4927";
} else {
mips_machtype = MACH_TOSHIBA_RBTX4937;
- toshiba_name = "TX4937";
+ toshiba_name = "TX4937";
}
msize = tx4927_get_mem_size();
for (i = 0; i < 8; i++) {
if (!(tx4938_ebuscptr->cr[i] & 0x8))
continue; /* disabled */
- rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i);
+ rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i);
txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i));
}
switch (current_cpu_data.cputype) {
case CPU_VR4111:
if (!(clkspeed & DIV2B))
- tclock = pclock / 2;
+ tclock = pclock / 2;
else if (!(clkspeed & DIV3B))
- tclock = pclock / 3;
+ tclock = pclock / 3;
else if (!(clkspeed & DIV4B))
- tclock = pclock / 4;
+ tclock = pclock / 4;
break;
case CPU_VR4121:
tclock = pclock / DIVT(clkspeed);
/* fixme */
#define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f))
#define pgoff_to_pte(off) \
- ((pte_t){(((off) & 0x3f) + ((off) << 6) + _PAGE_FILE)})
+ ((pte_t){(((off) & 0x3f) + ((off) << 6) + _PAGE_FILE)})
#else
#define pte_to_pgoff(_pte) \
#define ENABLE_BOARD 0x01
#define FAILED_BOARD 0x02
#define DUPLICATE_BOARD 0x04 /* Boards like midplanes/routers which
- are discovered twice. Use one of them */
+ are discovered twice. Use one of them */
#define VISITED_BOARD 0x08 /* Used for compact hub numbering. */
#define LOCAL_MASTER_IO6 0x10 /* master io6 for that node */
#define GLOBAL_MASTER_IO6 0x20
icsr_llp_en: 1, /* LLP enable bit */
icsr_rsvd2: 1, /* reserver */
icsr_wrm_reset: 1, /* Warm reset bit */
- icsr_rsvd1: 2, /* Data ready offset */
+ icsr_rsvd1: 2, /* Data ready offset */
icsr_null_to: 6; /* Null timeout */
} icsr_fields_s;
u64 perf_sel_reg;
struct {
u64 perf_rsvd : 48,
- perf_icct : 8,
- perf_ippr1 : 4,
- perf_ippr0 : 4;
+ perf_icct : 8,
+ perf_ippr1 : 4,
+ perf_ippr0 : 4;
} perf_sel_bits;
} io_perf_sel_t;
u64 perf_cnt;
struct {
u64 perf_rsvd1 : 32,
- perf_rsvd2 : 12,
- perf_cnt : 20;
+ perf_rsvd2 : 12,
+ perf_cnt : 20;
} perf_cnt_bits;
} io_perf_cnt_t;
int preempt_count; /* 0 => preemptable, <0 => BUG */
mm_segment_t addr_limit; /* thread address space:
- 0-0xBFFFFFFF for user-thead
+ 0-0xBFFFFFFF for user-thead
0-0xFFFFFFFF for kernel-thread
*/
struct restart_block restart_block;
projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / commitdiff