drm: rcar-du: Fix dot clock routing configuration

Dot clock routing is setup through different registers depending on the
DU generation. The code has been designed for Gen2 and hasn't been
updated since. This works thanks to good reset default value, but isn't
very safe. Fix it.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c
index 33b2fc53da3e3e35eefd7c71d6e07df483fa3f10..64738fca96d04acfa0515a020f24ffa07dea036c 100644 (file)
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
@@ -105,16 +105,20 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp)
        if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_EXT_CTRL_REGS)) {
                rcar_du_group_setup_defr8(rgrp);
 
-               /* Configure input dot clock routing. We currently hardcode the
-                * configuration to routing DOTCLKINn to DUn.
+               /*
+                * Configure input dot clock routing. We currently hardcode the
+                * configuration to routing DOTCLKINn to DUn. Register fields
+                * depend on the DU generation, but the resulting value is 0 in
+                * all cases.
+                *
+                * On Gen2 a single register in the first group controls dot
+                * clock selection for all channels, while on Gen3 dot clocks
+                * are setup through per-group registers, only available when
+                * the group has two channels.
                 */
-               rcar_du_group_write(rgrp, DIDSR, DIDSR_CODE |
-                                   DIDSR_LCDS_DCLKIN(2) |
-                                   DIDSR_LCDS_DCLKIN(1) |
-                                   DIDSR_LCDS_DCLKIN(0) |
-                                   DIDSR_PDCS_CLK(2, 0) |
-                                   DIDSR_PDCS_CLK(1, 0) |
-                                   DIDSR_PDCS_CLK(0, 0));
+               if ((rcdu->info->gen < 3 && rgrp->index == 0) ||
+                   (rcdu->info->gen == 3 &&  rgrp->num_crtcs > 1))
+                       rcar_du_group_write(rgrp, DIDSR, DIDSR_CODE);
        }
 
        if (rcdu->info->gen >= 3)