{ 1, 1, 3, 108, 205}, /* for 318.7 */
{ 2, 2, 3, 150, 215}, /* for 425.0 */
{ 3, 3, 3, 170, 253}, /* for 510.0 */
- { 4, 4, 3, 230, 256}, /* for 637.5 */
+ { 4, 4, 3, 230, 255}, /* for 637.5 */
{ 0, 0, 3, 0, 0}
};
.turbo_clock = 4, /* reserved clock src. */
.def_clock = 2, /* gpu clock used most of time.*/
.cfg_clock = CFG_CLOCK, /* max gpu clock. */
+ .cfg_clock_bkup = CFG_CLOCK,
.cfg_min_clock = CFG_MIN_CLOCK,
.sc_mpp = 3, /* number of pp used most of time.*/
int get_mali_freq_level(int freq)
{
- int i = 0, level = -1;
int mali_freq_num;
+ int i = 0, level = -1;
if(freq < 0)
return level;
+
mali_freq_num = mali_plat_data.dvfs_table_size - 1;
if(freq <= mali_plat_data.clk_sample[0])
level = mali_freq_num-1;
return;
if (idx > mali_plat_data.turbo_clock || idx < mali_plat_data.scale_info.minclk)
return;
-
mali_plat_data.scale_info.maxclk= idx;
revise_mali_rt();
}
struct mali_pmu_core *pmu;
ret = 0;
+ mali_pm_statue = 1;
device = (struct device *)param;
pmu = mali_pmu_get_global_pmu_core();
/* Need to notify Mali driver about this event */
ret = device->driver->pm->runtime_resume(device);
}
+ mali_pm_statue = 0;
return ret;
}
/* clock scaling. Kasin..*/
ret = mali_clock_critical(mali_cri_light_suspend, (size_t)device);
-
+ disable_clock();
return ret;
}
int mali_light_resume(struct device *device)
{
int ret = 0;
-
+ enable_clock();
ret = mali_clock_critical(mali_cri_light_resume, (size_t)device);
#ifdef CONFIG_MALI400_PROFILING
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
vh264_4k2k_register_module_callback(mali_4k2k_enter, mali_4k2k_exit);
#endif /* CONFIG_AM_VDEC_H264_4K2K */
}
-