drm/i915/bxt: IPC WA for Broxton
authorMahesh Kumar <mahesh1.kumar@intel.com>
Thu, 1 Dec 2016 15:49:34 +0000 (21:19 +0530)
committerPaulo Zanoni <paulo.r.zanoni@intel.com>
Wed, 7 Dec 2016 18:30:34 +0000 (16:30 -0200)
Display Workarounds #1135
If IPC is enabled in BXT, display underruns are observed.
WA: The Line Time programmed in the WM_LINETIME register should be
half of the actual calculated Line Time.

Programmed Line Time = 1/2*Calculated Line Time

Changes since V1:
 - Add Workaround number in commit & code
Changes since V2 (from Paulo):
 - Bikeshed white space and make the WA tag look like the others

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161201154940.24446-3-mahesh1.kumar@intel.com
drivers/gpu/drm/i915/i915_drv.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/intel_pm.c

index 5fe27e42d81be1184a41d1af612eb123f13d4bd2..d2cc28f6953db04421df03fe66f9bf99f891455e 100644 (file)
@@ -1239,6 +1239,8 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
 
        intel_runtime_pm_enable(dev_priv);
 
+       dev_priv->ipc_enabled = false;
+
        /* Everything is in place, we can now relax! */
        DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
                 driver.name, driver.major, driver.minor, driver.patchlevel,
index 33758ac5ec9a70bcc78f9608530c3d8d776b0d6f..4eea9255dc5329fbb8f6be5457d0dcd15558be6d 100644 (file)
@@ -2329,6 +2329,8 @@ struct drm_i915_private {
        /* perform PHY state sanity checks? */
        bool chv_phy_assert[2];
 
+       bool ipc_enabled;
+
        /* Used to save the pipe-to-encoder mapping for audio */
        struct intel_encoder *av_enc_map[I915_MAX_PIPES];
 
index 4db68459fd1872366f9067b536b1a16e80d8af83..9ea3eeed3385fbc5857500a7cc01d0d89713f60c 100644 (file)
@@ -3761,7 +3761,10 @@ skl_compute_wm_level(const struct drm_i915_private *dev_priv,
 static uint32_t
 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
 {
+       struct drm_atomic_state *state = cstate->base.state;
+       struct drm_i915_private *dev_priv = to_i915(state->dev);
        uint32_t pixel_rate;
+       uint32_t linetime_wm;
 
        if (!cstate->base.active)
                return 0;
@@ -3771,8 +3774,14 @@ skl_compute_linetime_wm(struct intel_crtc_state *cstate)
        if (WARN_ON(pixel_rate == 0))
                return 0;
 
-       return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
-                           pixel_rate);
+       linetime_wm = DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal *
+                                  1000, pixel_rate);
+
+       /* Display WA #1135: bxt. */
+       if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled)
+               linetime_wm = DIV_ROUND_UP(linetime_wm, 2);
+
+       return linetime_wm;
 }
 
 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,