drm/i915: Round-up clock and limit drain latency

Round up clock computation and limit drain latency to maximum of 0x7F.

Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index de27439636e85520b305b11e72446619a0e8286a..19bd7212f4a24c29ff217161a227a2256f4dba3c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1285,11 +1285,14 @@ static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
        if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
                return false;
 
-       entries = (clock / 1000) * pixel_size;
+       entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
        *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
                                       DRAIN_LATENCY_PRECISION_32;
        *drain_latency = (64 * (*prec_mult) * 4) / entries;
 
+       if (*drain_latency > DRAIN_LATENCY_MASK)
+               *drain_latency = DRAIN_LATENCY_MASK;
+
        return true;
 }