clk: mmp: add fixed clock UBS_PLL for pxa910/pxa168
authorChao Xie <chao.xie@marvell.com>
Thu, 30 Apr 2015 01:53:40 +0000 (09:53 +0800)
committerStephen Boyd <sboyd@codeaurora.org>
Thu, 4 Jun 2015 19:07:33 +0000 (12:07 -0700)
USB will drive clock from USB_PLL.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/mmp/clk-of-pxa168.c
drivers/clk/mmp/clk-of-pxa910.c
include/dt-bindings/clock/marvell,pxa168.h
include/dt-bindings/clock/marvell,pxa910.h

index 5b1810dc4bd20839d90531c6a47208a7f73a829f..01a650e6f8a43fd0db2e01f8925384d4c59c0c26 100644 (file)
@@ -58,6 +58,7 @@ static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
        {PXA168_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},
        {PXA168_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
        {PXA168_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 624000000},
+       {PXA168_CLK_USB_PLL, "usb_pll", NULL, CLK_IS_ROOT, 480000000},
 };
 
 static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
index 5e3c80dad336e0ea1857f39be3ccccadf7b947f8..cca98eff641a1829ed7f3a2a6327b712f56a5a80 100644 (file)
@@ -57,6 +57,7 @@ static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
        {PXA910_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},
        {PXA910_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
        {PXA910_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 624000000},
+       {PXA910_CLK_USB_PLL, "usb_pll", NULL, CLK_IS_ROOT, 480000000},
 };
 
 static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
index 79630b9d74b81b4c81582d74fd5b74bbe037a455..84ce5de6c83d270c652c63baefd5d6070349f3a9 100644 (file)
@@ -19,6 +19,7 @@
 #define PXA168_CLK_PLL1_2_1_5          19
 #define PXA168_CLK_PLL1_3_16           20
 #define PXA168_CLK_UART_PLL            27
+#define PXA168_CLK_USB_PLL             28
 
 /* apb periphrals */
 #define PXA168_CLK_TWSI0               60
index 719cffb2bea207e43b9fe40498401e14bb7d9151..bea08b60298b7a3f3c7331ed3a34fc8d57749de4 100644 (file)
@@ -19,6 +19,7 @@
 #define PXA910_CLK_PLL1_2_1_5          19
 #define PXA910_CLK_PLL1_3_16           20
 #define PXA910_CLK_UART_PLL            27
+#define PXA910_CLK_USB_PLL             28
 
 /* apb periphrals */
 #define PXA910_CLK_TWSI0               60