Almost entirely taken from the 64-bit PowerPC PCI code.
This allowed to eliminate a ton of cruft from the sparc64
PCI layer.
Signed-off-by: David S. Miller <davem@davemloft.net>
-/* $Id: pci.c,v 1.39 2002/01/05 01:13:43 davem Exp $
- * pci.c: UltraSparc PCI controller support.
+/* pci.c: UltraSparc PCI controller support.
*
* Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
* Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
* Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
+ *
+ * OF tree based PCI bus probing taken from the PowerPC port
+ * with minor modifications, see there for credits.
*/
#include <linux/module.h>
pci_controller_scan(pci_controller_init);
}
+static unsigned long pci_parse_of_flags(u32 addr0)
+{
+ unsigned long flags = 0;
+
+ if (addr0 & 0x02000000) {
+ flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
+ flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
+ flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
+ if (addr0 & 0x40000000)
+ flags |= IORESOURCE_PREFETCH
+ | PCI_BASE_ADDRESS_MEM_PREFETCH;
+ } else if (addr0 & 0x01000000)
+ flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
+ return flags;
+}
+
+/* The of_device layer has translated all of the assigned-address properties
+ * into physical address resources, we only have to figure out the register
+ * mapping.
+ */
+static void pci_parse_of_addrs(struct of_device *op,
+ struct device_node *node,
+ struct pci_dev *dev)
+{
+ struct resource *op_res;
+ const u32 *addrs;
+ int proplen;
+
+ addrs = of_get_property(node, "assigned-addresses", &proplen);
+ if (!addrs)
+ return;
+ printk(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
+ op_res = &op->resource[0];
+ for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
+ struct resource *res;
+ unsigned long flags;
+ int i;
+
+ flags = pci_parse_of_flags(addrs[0]);
+ if (!flags)
+ continue;
+ i = addrs[0] & 0xff;
+ printk(" start: %lx, end: %lx, i: %x\n",
+ op_res->start, op_res->end, i);
+
+ if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
+ res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
+ } else if (i == dev->rom_base_reg) {
+ res = &dev->resource[PCI_ROM_RESOURCE];
+ flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
+ } else {
+ printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
+ continue;
+ }
+ res->start = op_res->start;
+ res->end = op_res->end;
+ res->flags = flags;
+ res->name = pci_name(dev);
+ }
+}
+
+struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
+ struct device_node *node,
+ struct pci_bus *bus, int devfn)
+{
+ struct dev_archdata *sd;
+ struct pci_dev *dev;
+ const char *type;
+
+ dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
+ if (!dev)
+ return NULL;
+
+ sd = &dev->dev.archdata;
+ sd->iommu = pbm->iommu;
+ sd->stc = &pbm->stc;
+ sd->host_controller = pbm;
+ sd->prom_node = node;
+ sd->op = of_find_device_by_node(node);
+ sd->msi_num = 0xffffffff;
+
+ type = of_get_property(node, "device_type", NULL);
+ if (type == NULL)
+ type = "";
+
+ printk(" create device, devfn: %x, type: %s\n", devfn, type);
+
+ dev->bus = bus;
+ dev->sysdata = node;
+ dev->dev.parent = bus->bridge;
+ dev->dev.bus = &pci_bus_type;
+ dev->devfn = devfn;
+ dev->multifunction = 0; /* maybe a lie? */
+
+ dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
+ dev->device = of_getintprop_default(node, "device-id", 0xffff);
+ dev->subsystem_vendor =
+ of_getintprop_default(node, "subsystem-vendor-id", 0);
+ dev->subsystem_device =
+ of_getintprop_default(node, "subsystem-id", 0);
+
+ dev->cfg_size = pci_cfg_space_size(dev);
+
+ sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
+ dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
+ dev->class = of_getintprop_default(node, "class-code", 0);
+
+ printk(" class: 0x%x\n", dev->class);
+
+ dev->current_state = 4; /* unknown power state */
+ dev->error_state = pci_channel_io_normal;
+
+ if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
+ /* a PCI-PCI bridge */
+ dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
+ dev->rom_base_reg = PCI_ROM_ADDRESS1;
+ } else if (!strcmp(type, "cardbus")) {
+ dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
+ } else {
+ dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
+ dev->rom_base_reg = PCI_ROM_ADDRESS;
+
+ dev->irq = sd->op->irqs[0];
+ if (dev->irq == 0xffffffff)
+ dev->irq = PCI_IRQ_NONE;
+ }
+
+ pci_parse_of_addrs(sd->op, node, dev);
+
+ printk(" adding to system ...\n");
+
+ pci_device_add(dev, bus);
+
+ return dev;
+}
+
+static void __init pci_of_scan_bus(struct pci_pbm_info *pbm,
+ struct device_node *node,
+ struct pci_bus *bus);
+
+#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
+
+void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
+ struct device_node *node,
+ struct pci_dev *dev)
+{
+ struct pci_bus *bus;
+ const u32 *busrange, *ranges;
+ int len, i;
+ struct resource *res;
+ unsigned int flags;
+ u64 size;
+
+ printk("of_scan_pci_bridge(%s)\n", node->full_name);
+
+ /* parse bus-range property */
+ busrange = of_get_property(node, "bus-range", &len);
+ if (busrange == NULL || len != 8) {
+ printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
+ node->full_name);
+ return;
+ }
+ ranges = of_get_property(node, "ranges", &len);
+ if (ranges == NULL) {
+ printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
+ node->full_name);
+ return;
+ }
+
+ bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
+ if (!bus) {
+ printk(KERN_ERR "Failed to create pci bus for %s\n",
+ node->full_name);
+ return;
+ }
+
+ bus->primary = dev->bus->number;
+ bus->subordinate = busrange[1];
+ bus->bridge_ctl = 0;
+
+ /* parse ranges property */
+ /* PCI #address-cells == 3 and #size-cells == 2 always */
+ res = &dev->resource[PCI_BRIDGE_RESOURCES];
+ for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
+ res->flags = 0;
+ bus->resource[i] = res;
+ ++res;
+ }
+ i = 1;
+ for (; len >= 32; len -= 32, ranges += 8) {
+ struct resource *root;
+
+ flags = pci_parse_of_flags(ranges[0]);
+ size = GET_64BIT(ranges, 6);
+ if (flags == 0 || size == 0)
+ continue;
+ if (flags & IORESOURCE_IO) {
+ res = bus->resource[0];
+ if (res->flags) {
+ printk(KERN_ERR "PCI: ignoring extra I/O range"
+ " for bridge %s\n", node->full_name);
+ continue;
+ }
+ root = &pbm->io_space;
+ } else {
+ if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
+ printk(KERN_ERR "PCI: too many memory ranges"
+ " for bridge %s\n", node->full_name);
+ continue;
+ }
+ res = bus->resource[i];
+ ++i;
+ root = &pbm->mem_space;
+ }
+
+ res->start = GET_64BIT(ranges, 1);
+ res->end = res->start + size - 1;
+ res->flags = flags;
+
+ /* Another way to implement this would be to add an of_device
+ * layer routine that can calculate a resource for a given
+ * range property value in a PCI device.
+ */
+ pbm->parent->resource_adjust(dev, res, root);
+ }
+ sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
+ bus->number);
+ printk(" bus name: %s\n", bus->name);
+
+ pci_of_scan_bus(pbm, node, bus);
+}
+
+static void __init pci_of_scan_bus(struct pci_pbm_info *pbm,
+ struct device_node *node,
+ struct pci_bus *bus)
+{
+ struct device_node *child;
+ const u32 *reg;
+ int reglen, devfn;
+ struct pci_dev *dev;
+
+ printk("PCI: scan_bus[%s] bus no %d\n",
+ node->full_name, bus->number);
+
+ child = NULL;
+ while ((child = of_get_next_child(node, child)) != NULL) {
+ printk(" * %s\n", child->full_name);
+ reg = of_get_property(child, "reg", ®len);
+ if (reg == NULL || reglen < 20)
+ continue;
+ devfn = (reg[0] >> 8) & 0xff;
+
+ /* create a new pci_dev for this device */
+ dev = of_create_pci_dev(pbm, child, bus, devfn);
+ if (!dev)
+ continue;
+ printk("PCI: dev header type: %x\n", dev->hdr_type);
+
+ if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
+ dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
+ of_scan_pci_bridge(pbm, child, dev);
+ }
+}
+
+static ssize_t
+show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
+{
+ struct pci_dev *pdev;
+ struct device_node *dp;
+
+ pdev = to_pci_dev(dev);
+ dp = pdev->dev.archdata.prom_node;
+
+ return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
+}
+
+static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
+
+static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
+{
+ struct pci_dev *dev;
+ int err;
+
+ list_for_each_entry(dev, &bus->devices, bus_list) {
+ /* we don't really care if we can create this file or
+ * not, but we need to assign the result of the call
+ * or the world will fall under alien invasion and
+ * everybody will be frozen on a spaceship ready to be
+ * eaten on alpha centauri by some green and jelly
+ * humanoid.
+ */
+ err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
+ }
+}
+
+struct pci_bus * __init pci_scan_one_pbm(struct pci_pbm_info *pbm)
+{
+ struct pci_controller_info *p = pbm->parent;
+ struct device_node *node = pbm->prom_node;
+ struct pci_bus *bus;
+
+ printk("PCI: Scanning PBM %s\n", node->full_name);
+
+ /* XXX parent device? XXX */
+ bus = pci_create_bus(NULL, pbm->pci_first_busno, p->pci_ops, pbm);
+ if (!bus) {
+ printk(KERN_ERR "Failed to create bus for %s\n",
+ node->full_name);
+ return NULL;
+ }
+ bus->secondary = pbm->pci_first_busno;
+ bus->subordinate = pbm->pci_last_busno;
+
+ bus->resource[0] = &pbm->io_space;
+ bus->resource[1] = &pbm->mem_space;
+
+ pci_of_scan_bus(pbm, node, bus);
+ pci_bus_add_devices(bus);
+ pci_bus_register_of_sysfs(bus);
+
+ return bus;
+}
+
static void __init pci_scan_each_controller_bus(void)
{
struct pci_controller_info *p;
{
}
-int pcibios_enable_device(struct pci_dev *pdev, int mask)
+int pcibios_enable_device(struct pci_dev *dev, int mask)
{
+ u16 cmd, oldcmd;
+ int i;
+
+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
+ oldcmd = cmd;
+
+ for (i = 0; i < PCI_NUM_RESOURCES; i++) {
+ struct resource *res = &dev->resource[i];
+
+ /* Only set up the requested stuff */
+ if (!(mask & (1<<i)))
+ continue;
+
+ if (res->flags & IORESOURCE_IO)
+ cmd |= PCI_COMMAND_IO;
+ if (res->flags & IORESOURCE_MEM)
+ cmd |= PCI_COMMAND_MEMORY;
+ }
+
+ if (cmd != oldcmd) {
+ printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
+ pci_name(dev), cmd);
+ /* Enable the appropriate bits in the PCI command register. */
+ pci_write_config_word(dev, PCI_COMMAND, cmd);
+ }
return 0;
}
static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
enum pci_mmap_state mmap_state)
{
- struct pcidev_cookie *pcp = pdev->sysdata;
- struct pci_pbm_info *pbm;
+ struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
struct pci_controller_info *p;
unsigned long space_size, user_offset, user_size;
- if (!pcp)
- return -ENXIO;
- pbm = pcp->pbm;
- if (!pbm)
- return -ENXIO;
-
p = pbm->parent;
if (p->pbms_same_domain) {
unsigned long lowest, highest;
#ifdef CONFIG_PCI_MSI
int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
{
- struct pcidev_cookie *pcp = pdev->sysdata;
- struct pci_pbm_info *pbm = pcp->pbm;
+ struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
struct pci_controller_info *p = pbm->parent;
int virt_irq, err;
{
struct msi_desc *entry = get_irq_msi(virt_irq);
struct pci_dev *pdev = entry->dev;
- struct pcidev_cookie *pcp = pdev->sysdata;
- struct pci_pbm_info *pbm = pcp->pbm;
+ struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
struct pci_controller_info *p = pbm->parent;
if (!pbm->msi_num || !p->setup_msi_irq)
struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
{
- struct pcidev_cookie *pc = pdev->sysdata;
-
- return pc->op->node;
+ return pdev->dev.archdata.prom_node;
}
EXPORT_SYMBOL(pci_device_to_OF_node);
#include "pci_impl.h"
-/* Fix self device of BUS and hook it into BUS->self.
- * The pci_scan_bus does not do this for the host bridge.
- */
-void __init pci_fixup_host_bridge_self(struct pci_bus *pbus)
-{
- struct pci_dev *pdev;
-
- list_for_each_entry(pdev, &pbus->devices, bus_list) {
- if (pdev->class >> 8 == PCI_CLASS_BRIDGE_HOST) {
- pbus->self = pdev;
- return;
- }
- }
-
- prom_printf("PCI: Critical error, cannot find host bridge PDEV.\n");
- prom_halt();
-}
-
-/* Find the OBP PROM device tree node for a PCI device. */
-static struct device_node * __init
-find_device_prom_node(struct pci_pbm_info *pbm, struct pci_dev *pdev,
- struct device_node *bus_node,
- struct linux_prom_pci_registers **pregs,
- int *nregs)
-{
- struct device_node *dp;
-
- *nregs = 0;
-
- /*
- * Return the PBM's PROM node in case we are it's PCI device,
- * as the PBM's reg property is different to standard PCI reg
- * properties. We would delete this device entry otherwise,
- * which confuses XFree86's device probing...
- */
- if ((pdev->bus->number == pbm->pci_bus->number) && (pdev->devfn == 0) &&
- (pdev->vendor == PCI_VENDOR_ID_SUN) &&
- (pdev->device == PCI_DEVICE_ID_SUN_PBM ||
- pdev->device == PCI_DEVICE_ID_SUN_SCHIZO ||
- pdev->device == PCI_DEVICE_ID_SUN_TOMATILLO ||
- pdev->device == PCI_DEVICE_ID_SUN_SABRE ||
- pdev->device == PCI_DEVICE_ID_SUN_HUMMINGBIRD))
- return bus_node;
-
- dp = bus_node->child;
- while (dp) {
- struct linux_prom_pci_registers *regs;
- struct property *prop;
- int len;
-
- prop = of_find_property(dp, "reg", &len);
- if (!prop)
- goto do_next_sibling;
-
- regs = prop->value;
- if (((regs[0].phys_hi >> 8) & 0xff) == pdev->devfn) {
- *pregs = regs;
- *nregs = len / sizeof(struct linux_prom_pci_registers);
- return dp;
- }
-
- do_next_sibling:
- dp = dp->sibling;
- }
-
- return NULL;
-}
-
-/* Older versions of OBP on PCI systems encode 64-bit MEM
- * space assignments incorrectly, this fixes them up. We also
- * take the opportunity here to hide other kinds of bogus
- * assignments.
- */
-static void __init fixup_obp_assignments(struct pci_dev *pdev,
- struct pcidev_cookie *pcp)
-{
- int i;
-
- if (pdev->vendor == PCI_VENDOR_ID_AL &&
- (pdev->device == PCI_DEVICE_ID_AL_M7101 ||
- pdev->device == PCI_DEVICE_ID_AL_M1533)) {
- int i;
-
- /* Zap all of the normal resources, they are
- * meaningless and generate bogus resource collision
- * messages. This is OpenBoot's ill-fated attempt to
- * represent the implicit resources that these devices
- * have.
- */
- pcp->num_prom_assignments = 0;
- for (i = 0; i < 6; i++) {
- pdev->resource[i].start =
- pdev->resource[i].end =
- pdev->resource[i].flags = 0;
- }
- pdev->resource[PCI_ROM_RESOURCE].start =
- pdev->resource[PCI_ROM_RESOURCE].end =
- pdev->resource[PCI_ROM_RESOURCE].flags = 0;
- return;
- }
-
- for (i = 0; i < pcp->num_prom_assignments; i++) {
- struct linux_prom_pci_registers *ap;
- int space;
-
- ap = &pcp->prom_assignments[i];
- space = ap->phys_hi >> 24;
- if ((space & 0x3) == 2 &&
- (space & 0x4) != 0) {
- ap->phys_hi &= ~(0x7 << 24);
- ap->phys_hi |= 0x3 << 24;
- }
- }
-}
-
-static ssize_t
-show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
-{
- struct pci_dev *pdev;
- struct pcidev_cookie *sysdata;
-
- pdev = to_pci_dev(dev);
- sysdata = pdev->sysdata;
-
- return snprintf (buf, PAGE_SIZE, "%s\n", sysdata->prom_node->full_name);
-}
-
-static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
-
-/* Fill in the PCI device cookie sysdata for the given
- * PCI device. This cookie is the means by which one
- * can get to OBP and PCI controller specific information
- * for a PCI device.
- */
-static void __init pdev_cookie_fillin(struct pci_pbm_info *pbm,
- struct pci_dev *pdev,
- struct device_node *bus_node)
-{
- struct linux_prom_pci_registers *pregs = NULL;
- struct pcidev_cookie *pcp;
- struct device_node *dp;
- struct property *prop;
- int nregs, len, err;
-
- dp = find_device_prom_node(pbm, pdev, bus_node,
- &pregs, &nregs);
- if (!dp) {
- /* If it is not in the OBP device tree then
- * there must be a damn good reason for it.
- *
- * So what we do is delete the device from the
- * PCI device tree completely. This scenario
- * is seen, for example, on CP1500 for the
- * second EBUS/HappyMeal pair if the external
- * connector for it is not present.
- */
- pci_remove_bus_device(pdev);
- return;
- }
-
- pcp = kzalloc(sizeof(*pcp), GFP_ATOMIC);
- if (pcp == NULL) {
- prom_printf("PCI_COOKIE: Fatal malloc error, aborting...\n");
- prom_halt();
- }
- pcp->pbm = pbm;
- pcp->prom_node = dp;
- pcp->op = of_find_device_by_node(dp);
- memcpy(pcp->prom_regs, pregs,
- nregs * sizeof(struct linux_prom_pci_registers));
- pcp->num_prom_regs = nregs;
-
- /* We can't have the pcidev_cookie assignments be just
- * direct pointers into the property value, since they
- * are potentially modified by the probing process.
- */
- prop = of_find_property(dp, "assigned-addresses", &len);
- if (!prop) {
- pcp->num_prom_assignments = 0;
- } else {
- memcpy(pcp->prom_assignments, prop->value, len);
- pcp->num_prom_assignments =
- (len / sizeof(pcp->prom_assignments[0]));
- }
-
- if (strcmp(dp->name, "ebus") == 0) {
- struct linux_prom_ebus_ranges *erng;
- int iter;
-
- /* EBUS is special... */
- prop = of_find_property(dp, "ranges", &len);
- if (!prop) {
- prom_printf("EBUS: Fatal error, no range property\n");
- prom_halt();
- }
- erng = prop->value;
- len = (len / sizeof(erng[0]));
- for (iter = 0; iter < len; iter++) {
- struct linux_prom_ebus_ranges *ep = &erng[iter];
- struct linux_prom_pci_registers *ap;
-
- ap = &pcp->prom_assignments[iter];
-
- ap->phys_hi = ep->parent_phys_hi;
- ap->phys_mid = ep->parent_phys_mid;
- ap->phys_lo = ep->parent_phys_lo;
- ap->size_hi = 0;
- ap->size_lo = ep->size;
- }
- pcp->num_prom_assignments = len;
- }
-
- fixup_obp_assignments(pdev, pcp);
-
- pdev->sysdata = pcp;
-
- /* we don't really care if we can create this file or not,
- * but we need to assign the result of the call or the world will fall
- * under alien invasion and everybody will be frozen on a spaceship
- * ready to be eaten on alpha centauri by some green and jelly humanoid.
- */
- err = sysfs_create_file(&pdev->dev.kobj, &dev_attr_obppath.attr);
-}
-
-void __init pci_fill_in_pbm_cookies(struct pci_bus *pbus,
- struct pci_pbm_info *pbm,
- struct device_node *dp)
-{
- struct pci_dev *pdev, *pdev_next;
- struct pci_bus *this_pbus, *pbus_next;
-
- /* This must be _safe because the cookie fillin
- routine can delete devices from the tree. */
- list_for_each_entry_safe(pdev, pdev_next, &pbus->devices, bus_list)
- pdev_cookie_fillin(pbm, pdev, dp);
-
- list_for_each_entry_safe(this_pbus, pbus_next, &pbus->children, node) {
- struct pcidev_cookie *pcp = this_pbus->self->sysdata;
-
- pci_fill_in_pbm_cookies(this_pbus, pbm, pcp->prom_node);
- }
-}
-
-static void __init bad_assignment(struct pci_dev *pdev,
- struct linux_prom_pci_registers *ap,
- struct resource *res,
- int do_prom_halt)
-{
- prom_printf("PCI: Bogus PROM assignment. BUS[%02x] DEVFN[%x]\n",
- pdev->bus->number, pdev->devfn);
- if (ap)
- prom_printf("PCI: phys[%08x:%08x:%08x] size[%08x:%08x]\n",
- ap->phys_hi, ap->phys_mid, ap->phys_lo,
- ap->size_hi, ap->size_lo);
- if (res)
- prom_printf("PCI: RES[%016lx-->%016lx:(%lx)]\n",
- res->start, res->end, res->flags);
- if (do_prom_halt)
- prom_halt();
-}
-
-static struct resource *
-__init get_root_resource(struct linux_prom_pci_registers *ap,
- struct pci_pbm_info *pbm)
-{
- int space = (ap->phys_hi >> 24) & 3;
-
- switch (space) {
- case 0:
- /* Configuration space, silently ignore it. */
- return NULL;
-
- case 1:
- /* 16-bit IO space */
- return &pbm->io_space;
-
- case 2:
- /* 32-bit MEM space */
- return &pbm->mem_space;
-
- case 3:
- /* 64-bit MEM space, these are allocated out of
- * the 32-bit mem_space range for the PBM, ie.
- * we just zero out the upper 32-bits.
- */
- return &pbm->mem_space;
-
- default:
- printk("PCI: What is resource space %x?\n", space);
- return NULL;
- };
-}
-
-static struct resource *
-__init get_device_resource(struct linux_prom_pci_registers *ap,
- struct pci_dev *pdev)
-{
- struct resource *res;
- int breg = (ap->phys_hi & 0xff);
-
- switch (breg) {
- case PCI_ROM_ADDRESS:
- /* Unfortunately I have seen several cases where
- * buggy FCODE uses a space value of '1' (I/O space)
- * in the register property for the ROM address
- * so disable this sanity check for now.
- */
-#if 0
- {
- int space = (ap->phys_hi >> 24) & 3;
-
- /* It had better be MEM space. */
- if (space != 2)
- bad_assignment(pdev, ap, NULL, 0);
- }
-#endif
- res = &pdev->resource[PCI_ROM_RESOURCE];
- break;
-
- case PCI_BASE_ADDRESS_0:
- case PCI_BASE_ADDRESS_1:
- case PCI_BASE_ADDRESS_2:
- case PCI_BASE_ADDRESS_3:
- case PCI_BASE_ADDRESS_4:
- case PCI_BASE_ADDRESS_5:
- res = &pdev->resource[(breg - PCI_BASE_ADDRESS_0) / 4];
- break;
-
- default:
- bad_assignment(pdev, ap, NULL, 0);
- res = NULL;
- break;
- };
-
- return res;
-}
-
-static void __init pdev_record_assignments(struct pci_pbm_info *pbm,
- struct pci_dev *pdev)
-{
- struct pcidev_cookie *pcp = pdev->sysdata;
- int i;
-
- for (i = 0; i < pcp->num_prom_assignments; i++) {
- struct linux_prom_pci_registers *ap;
- struct resource *root, *res;
-
- /* The format of this property is specified in
- * the PCI Bus Binding to IEEE1275-1994.
- */
- ap = &pcp->prom_assignments[i];
- root = get_root_resource(ap, pbm);
- res = get_device_resource(ap, pdev);
- if (root == NULL || res == NULL ||
- res->flags == 0)
- continue;
-
- /* Ok we know which resource this PROM assignment is
- * for, sanity check it.
- */
- if ((res->start & 0xffffffffUL) != ap->phys_lo)
- bad_assignment(pdev, ap, res, 1);
-
- /* If it is a 64-bit MEM space assignment, verify that
- * the resource is too and that the upper 32-bits match.
- */
- if (((ap->phys_hi >> 24) & 3) == 3) {
- if (((res->flags & IORESOURCE_MEM) == 0) ||
- ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
- != PCI_BASE_ADDRESS_MEM_TYPE_64))
- bad_assignment(pdev, ap, res, 1);
- if ((res->start >> 32) != ap->phys_mid)
- bad_assignment(pdev, ap, res, 1);
-
- /* PBM cannot generate cpu initiated PIOs
- * to the full 64-bit space. Therefore the
- * upper 32-bits better be zero. If it is
- * not, just skip it and we will assign it
- * properly ourselves.
- */
- if ((res->start >> 32) != 0UL) {
- printk(KERN_ERR "PCI: OBP assigns out of range MEM address "
- "%016lx for region %ld on device %s\n",
- res->start, (res - &pdev->resource[0]), pci_name(pdev));
- continue;
- }
- }
-
- /* Adjust the resource into the physical address space
- * of this PBM.
- */
- pbm->parent->resource_adjust(pdev, res, root);
-
- if (request_resource(root, res) < 0) {
- int rnum;
-
- /* OK, there is some conflict. But this is fine
- * since we'll reassign it in the fixup pass.
- *
- * Do not print the warning for ROM resources
- * as such a conflict is quite common and
- * harmless as the ROM bar is disabled.
- */
- rnum = (res - &pdev->resource[0]);
- if (rnum != PCI_ROM_RESOURCE)
- printk(KERN_ERR "PCI: Resource collision, "
- "region %d "
- "[%016lx:%016lx] of device %s\n",
- rnum,
- res->start, res->end,
- pci_name(pdev));
- }
- }
-}
-
-void __init pci_record_assignments(struct pci_pbm_info *pbm,
- struct pci_bus *pbus)
-{
- struct pci_dev *dev;
- struct pci_bus *bus;
-
- list_for_each_entry(dev, &pbus->devices, bus_list)
- pdev_record_assignments(pbm, dev);
-
- list_for_each_entry(bus, &pbus->children, node)
- pci_record_assignments(pbm, bus);
-}
-
-/* Return non-zero if PDEV has implicit I/O resources even
- * though it may not have an I/O base address register
- * active.
- */
-static int __init has_implicit_io(struct pci_dev *pdev)
-{
- int class = pdev->class >> 8;
-
- if (class == PCI_CLASS_NOT_DEFINED ||
- class == PCI_CLASS_NOT_DEFINED_VGA ||
- class == PCI_CLASS_STORAGE_IDE ||
- (pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
- return 1;
-
- return 0;
-}
-
-static void __init pdev_assign_unassigned(struct pci_pbm_info *pbm,
- struct pci_dev *pdev)
-{
- u32 reg;
- u16 cmd;
- int i, io_seen, mem_seen;
-
- io_seen = mem_seen = 0;
- for (i = 0; i < PCI_NUM_RESOURCES; i++) {
- struct resource *root, *res;
- unsigned long size, min, max, align;
-
- res = &pdev->resource[i];
-
- if (res->flags & IORESOURCE_IO)
- io_seen++;
- else if (res->flags & IORESOURCE_MEM)
- mem_seen++;
-
- /* If it is already assigned or the resource does
- * not exist, there is nothing to do.
- */
- if (res->parent != NULL || res->flags == 0UL)
- continue;
-
- /* Determine the root we allocate from. */
- if (res->flags & IORESOURCE_IO) {
- root = &pbm->io_space;
- min = root->start + 0x400UL;
- max = root->end;
- } else {
- root = &pbm->mem_space;
- min = root->start;
- max = min + 0x80000000UL;
- }
-
- size = res->end - res->start;
- align = size + 1;
- if (allocate_resource(root, res, size + 1, min, max, align, NULL, NULL) < 0) {
- /* uh oh */
- prom_printf("PCI: Failed to allocate resource %d for %s\n",
- i, pci_name(pdev));
- prom_halt();
- }
-
- /* Update PCI config space. */
- pbm->parent->base_address_update(pdev, i);
- }
-
- /* Special case, disable the ROM. Several devices
- * act funny (ie. do not respond to memory space writes)
- * when it is left enabled. A good example are Qlogic,ISP
- * adapters.
- */
- pci_read_config_dword(pdev, PCI_ROM_ADDRESS, ®);
- reg &= ~PCI_ROM_ADDRESS_ENABLE;
- pci_write_config_dword(pdev, PCI_ROM_ADDRESS, reg);
-
- /* If we saw I/O or MEM resources, enable appropriate
- * bits in PCI command register.
- */
- if (io_seen || mem_seen) {
- pci_read_config_word(pdev, PCI_COMMAND, &cmd);
- if (io_seen || has_implicit_io(pdev))
- cmd |= PCI_COMMAND_IO;
- if (mem_seen)
- cmd |= PCI_COMMAND_MEMORY;
- pci_write_config_word(pdev, PCI_COMMAND, cmd);
- }
-
- /* If this is a PCI bridge or an IDE controller,
- * enable bus mastering. In the former case also
- * set the cache line size correctly.
- */
- if (((pdev->class >> 8) == PCI_CLASS_BRIDGE_PCI) ||
- (((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) &&
- ((pdev->class & 0x80) != 0))) {
- pci_read_config_word(pdev, PCI_COMMAND, &cmd);
- cmd |= PCI_COMMAND_MASTER;
- pci_write_config_word(pdev, PCI_COMMAND, cmd);
-
- if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
- pci_write_config_byte(pdev,
- PCI_CACHE_LINE_SIZE,
- (64 / sizeof(u32)));
- }
-}
-
-void __init pci_assign_unassigned(struct pci_pbm_info *pbm,
- struct pci_bus *pbus)
-{
- struct pci_dev *dev;
- struct pci_bus *bus;
-
- list_for_each_entry(dev, &pbus->devices, bus_list)
- pdev_assign_unassigned(pbm, dev);
-
- list_for_each_entry(bus, &pbus->children, node)
- pci_assign_unassigned(pbm, bus);
-}
-
-static void __init pdev_fixup_irq(struct pci_dev *pdev)
-{
- struct pcidev_cookie *pcp = pdev->sysdata;
- struct of_device *op = pcp->op;
-
- if (op->irqs[0] == 0xffffffff) {
- pdev->irq = PCI_IRQ_NONE;
- return;
- }
-
- pdev->irq = op->irqs[0];
-
- pci_write_config_byte(pdev, PCI_INTERRUPT_LINE,
- pdev->irq & PCI_IRQ_INO);
-}
-
-void __init pci_fixup_irq(struct pci_pbm_info *pbm,
- struct pci_bus *pbus)
-{
- struct pci_dev *dev;
- struct pci_bus *bus;
-
- list_for_each_entry(dev, &pbus->devices, bus_list)
- pdev_fixup_irq(dev);
-
- list_for_each_entry(bus, &pbus->children, node)
- pci_fixup_irq(pbm, bus);
-}
-
-static void pdev_setup_busmastering(struct pci_dev *pdev, int is_66mhz)
-{
- u16 cmd;
- u8 hdr_type, min_gnt, ltimer;
-
- pci_read_config_word(pdev, PCI_COMMAND, &cmd);
- cmd |= PCI_COMMAND_MASTER;
- pci_write_config_word(pdev, PCI_COMMAND, cmd);
-
- /* Read it back, if the mastering bit did not
- * get set, the device does not support bus
- * mastering so we have nothing to do here.
- */
- pci_read_config_word(pdev, PCI_COMMAND, &cmd);
- if ((cmd & PCI_COMMAND_MASTER) == 0)
- return;
-
- /* Set correct cache line size, 64-byte on all
- * Sparc64 PCI systems. Note that the value is
- * measured in 32-bit words.
- */
- pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
- 64 / sizeof(u32));
-
- pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr_type);
- hdr_type &= ~0x80;
- if (hdr_type != PCI_HEADER_TYPE_NORMAL)
- return;
-
- /* If the latency timer is already programmed with a non-zero
- * value, assume whoever set it (OBP or whoever) knows what
- * they are doing.
- */
- pci_read_config_byte(pdev, PCI_LATENCY_TIMER, <imer);
- if (ltimer != 0)
- return;
-
- /* XXX Since I'm tipping off the min grant value to
- * XXX choose a suitable latency timer value, I also
- * XXX considered making use of the max latency value
- * XXX as well. Unfortunately I've seen too many bogusly
- * XXX low settings for it to the point where it lacks
- * XXX any usefulness. In one case, an ethernet card
- * XXX claimed a min grant of 10 and a max latency of 5.
- * XXX Now, if I had two such cards on the same bus I
- * XXX could not set the desired burst period (calculated
- * XXX from min grant) without violating the max latency
- * XXX bound. Duh...
- * XXX
- * XXX I blame dumb PC bios implementors for stuff like
- * XXX this, most of them don't even try to do something
- * XXX sensible with latency timer values and just set some
- * XXX default value (usually 32) into every device.
- */
-
- pci_read_config_byte(pdev, PCI_MIN_GNT, &min_gnt);
-
- if (min_gnt == 0) {
- /* If no min_gnt setting then use a default
- * value.
- */
- if (is_66mhz)
- ltimer = 16;
- else
- ltimer = 32;
- } else {
- int shift_factor;
-
- if (is_66mhz)
- shift_factor = 2;
- else
- shift_factor = 3;
-
- /* Use a default value when the min_gnt value
- * is erroneously high.
- */
- if (((unsigned int) min_gnt << shift_factor) > 512 ||
- ((min_gnt << shift_factor) & 0xff) == 0) {
- ltimer = 8 << shift_factor;
- } else {
- ltimer = min_gnt << shift_factor;
- }
- }
-
- pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ltimer);
-}
-
-void pci_determine_66mhz_disposition(struct pci_pbm_info *pbm,
- struct pci_bus *pbus)
-{
- struct pci_dev *pdev;
- int all_are_66mhz;
- u16 status;
-
- if (pbm->is_66mhz_capable == 0) {
- all_are_66mhz = 0;
- goto out;
- }
-
- all_are_66mhz = 1;
- list_for_each_entry(pdev, &pbus->devices, bus_list) {
- pci_read_config_word(pdev, PCI_STATUS, &status);
- if (!(status & PCI_STATUS_66MHZ)) {
- all_are_66mhz = 0;
- break;
- }
- }
-out:
- pbm->all_devs_66mhz = all_are_66mhz;
-
- printk("PCI%d(PBM%c): Bus running at %dMHz\n",
- pbm->parent->index,
- (pbm == &pbm->parent->pbm_A) ? 'A' : 'B',
- (all_are_66mhz ? 66 : 33));
-}
-
-void pci_setup_busmastering(struct pci_pbm_info *pbm,
- struct pci_bus *pbus)
-{
- struct pci_dev *dev;
- struct pci_bus *bus;
- int is_66mhz;
-
- is_66mhz = pbm->is_66mhz_capable && pbm->all_devs_66mhz;
-
- list_for_each_entry(dev, &pbus->devices, bus_list)
- pdev_setup_busmastering(dev, is_66mhz);
-
- list_for_each_entry(bus, &pbus->children, node)
- pci_setup_busmastering(pbm, bus);
-}
-
void pci_register_legacy_regions(struct resource *io_res,
struct resource *mem_res)
{
extern int pci_num_controllers;
/* PCI bus scanning and fixup support. */
-extern void pci_fixup_host_bridge_self(struct pci_bus *pbus);
-extern void pci_fill_in_pbm_cookies(struct pci_bus *pbus,
- struct pci_pbm_info *pbm,
- struct device_node *prom_node);
-extern void pci_record_assignments(struct pci_pbm_info *pbm,
- struct pci_bus *pbus);
-extern void pci_assign_unassigned(struct pci_pbm_info *pbm,
- struct pci_bus *pbus);
-extern void pci_fixup_irq(struct pci_pbm_info *pbm,
- struct pci_bus *pbus);
-extern void pci_determine_66mhz_disposition(struct pci_pbm_info *pbm,
- struct pci_bus *pbus);
-extern void pci_setup_busmastering(struct pci_pbm_info *pbm,
- struct pci_bus *pbus);
+extern struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm);
extern void pci_register_legacy_regions(struct resource *io_res,
struct resource *mem_res);
*/
static void *pci_4u_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp, gfp_t gfp)
{
- struct pcidev_cookie *pcp;
struct pci_iommu *iommu;
iopte_t *iopte;
unsigned long flags, order, first_page;
return NULL;
memset((char *)first_page, 0, PAGE_SIZE << order);
- pcp = pdev->sysdata;
- iommu = pcp->pbm->iommu;
+ iommu = pdev->dev.archdata.iommu;
spin_lock_irqsave(&iommu->lock, flags);
iopte = alloc_npages(iommu, size >> IO_PAGE_SHIFT);
/* Free and unmap a consistent DMA translation. */
static void pci_4u_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
{
- struct pcidev_cookie *pcp;
struct pci_iommu *iommu;
iopte_t *iopte;
unsigned long flags, order, npages;
npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
- pcp = pdev->sysdata;
- iommu = pcp->pbm->iommu;
+ iommu = pdev->dev.archdata.iommu;
iopte = iommu->page_table +
((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
*/
static dma_addr_t pci_4u_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
{
- struct pcidev_cookie *pcp;
struct pci_iommu *iommu;
struct pci_strbuf *strbuf;
iopte_t *base;
u32 bus_addr, ret;
unsigned long iopte_protection;
- pcp = pdev->sysdata;
- iommu = pcp->pbm->iommu;
- strbuf = &pcp->pbm->stc;
+ iommu = pdev->dev.archdata.iommu;
+ strbuf = pdev->dev.archdata.stc;
if (unlikely(direction == PCI_DMA_NONE))
goto bad_no_ctx;
/* Unmap a single streaming mode DMA translation. */
static void pci_4u_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
{
- struct pcidev_cookie *pcp;
struct pci_iommu *iommu;
struct pci_strbuf *strbuf;
iopte_t *base;
return;
}
- pcp = pdev->sysdata;
- iommu = pcp->pbm->iommu;
- strbuf = &pcp->pbm->stc;
+ iommu = pdev->dev.archdata.iommu;
+ strbuf = pdev->dev.archdata.stc;
npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
npages >>= IO_PAGE_SHIFT;
*/
static int pci_4u_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
{
- struct pcidev_cookie *pcp;
struct pci_iommu *iommu;
struct pci_strbuf *strbuf;
unsigned long flags, ctx, npages, iopte_protection;
return 1;
}
- pcp = pdev->sysdata;
- iommu = pcp->pbm->iommu;
- strbuf = &pcp->pbm->stc;
+ iommu = pdev->dev.archdata.iommu;
+ strbuf = pdev->dev.archdata.stc;
if (unlikely(direction == PCI_DMA_NONE))
goto bad_no_ctx;
/* Unmap a set of streaming mode DMA translations. */
static void pci_4u_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
{
- struct pcidev_cookie *pcp;
struct pci_iommu *iommu;
struct pci_strbuf *strbuf;
iopte_t *base;
WARN_ON(1);
}
- pcp = pdev->sysdata;
- iommu = pcp->pbm->iommu;
- strbuf = &pcp->pbm->stc;
+ iommu = pdev->dev.archdata.iommu;
+ strbuf = pdev->dev.archdata.stc;
bus_addr = sglist->dma_address & IO_PAGE_MASK;
*/
static void pci_4u_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
{
- struct pcidev_cookie *pcp;
struct pci_iommu *iommu;
struct pci_strbuf *strbuf;
unsigned long flags, ctx, npages;
- pcp = pdev->sysdata;
- iommu = pcp->pbm->iommu;
- strbuf = &pcp->pbm->stc;
+ iommu = pdev->dev.archdata.iommu;
+ strbuf = pdev->dev.archdata.stc;
if (!strbuf->strbuf_enabled)
return;
*/
static void pci_4u_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
{
- struct pcidev_cookie *pcp;
struct pci_iommu *iommu;
struct pci_strbuf *strbuf;
unsigned long flags, ctx, npages, i;
u32 bus_addr;
- pcp = pdev->sysdata;
- iommu = pcp->pbm->iommu;
- strbuf = &pcp->pbm->stc;
+ iommu = pdev->dev.archdata.iommu;
+ strbuf = pdev->dev.archdata.stc;
if (!strbuf->strbuf_enabled)
return;
int pci_dma_supported(struct pci_dev *pdev, u64 device_mask)
{
- struct pcidev_cookie *pcp = pdev->sysdata;
u64 dma_addr_mask;
if (pdev == NULL) {
dma_addr_mask = 0xffffffff;
} else {
- struct pci_iommu *iommu = pcp->pbm->iommu;
+ struct pci_iommu *iommu = pdev->dev.archdata.iommu;
dma_addr_mask = iommu->dma_addr_mask;
static void psycho_base_address_update(struct pci_dev *pdev, int resource)
{
- struct pcidev_cookie *pcp = pdev->sysdata;
- struct pci_pbm_info *pbm = pcp->pbm;
+ struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
struct resource *res, *root;
u32 reg;
int where, size, is_64bit;
static void pbm_scan_bus(struct pci_controller_info *p,
struct pci_pbm_info *pbm)
{
- struct pcidev_cookie *cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
-
- if (!cookie) {
- prom_printf("PSYCHO: Critical allocation failure.\n");
- prom_halt();
- }
-
- /* All we care about is the PBM. */
- cookie->pbm = pbm;
-
- pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno,
- p->pci_ops,
- pbm);
- pci_fixup_host_bridge_self(pbm->pci_bus);
- pbm->pci_bus->self->sysdata = cookie;
-
- pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
- pci_record_assignments(pbm, pbm->pci_bus);
- pci_assign_unassigned(pbm, pbm->pci_bus);
- pci_fixup_irq(pbm, pbm->pci_bus);
- pci_determine_66mhz_disposition(pbm, pbm->pci_bus);
- pci_setup_busmastering(pbm, pbm->pci_bus);
+ pbm->pci_bus = pci_scan_one_pbm(pbm);
}
static void psycho_scan_bus(struct pci_controller_info *p)
p->index);
ret = IRQ_HANDLED;
}
- pci_read_config_word(sabre_root_bus->self,
- PCI_STATUS, &stat);
+ pci_bus_read_config_word(sabre_root_bus, 0,
+ PCI_STATUS, &stat);
if (stat & (PCI_STATUS_PARITY |
PCI_STATUS_SIG_TARGET_ABORT |
PCI_STATUS_REC_TARGET_ABORT |
PCI_STATUS_SIG_SYSTEM_ERROR)) {
printk("SABRE%d: PCI bus error, PCI_STATUS[%04x]\n",
p->index, stat);
- pci_write_config_word(sabre_root_bus->self,
- PCI_STATUS, 0xffff);
+ pci_bus_write_config_word(sabre_root_bus, 0,
+ PCI_STATUS, 0xffff);
ret = IRQ_HANDLED;
}
return ret;
static void sabre_base_address_update(struct pci_dev *pdev, int resource)
{
- struct pcidev_cookie *pcp = pdev->sysdata;
- struct pci_pbm_info *pbm = pcp->pbm;
+ struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
struct resource *res;
unsigned long base;
u32 reg;
}
}
-static struct pcidev_cookie *alloc_bridge_cookie(struct pci_pbm_info *pbm)
-{
- struct pcidev_cookie *cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
-
- if (!cookie) {
- prom_printf("SABRE: Critical allocation failure.\n");
- prom_halt();
- }
-
- /* All we care about is the PBM. */
- cookie->pbm = pbm;
-
- return cookie;
-}
-
static void sabre_scan_bus(struct pci_controller_info *p)
{
static int once;
struct pci_bus *sabre_bus, *pbus;
struct pci_pbm_info *pbm;
- struct pcidev_cookie *cookie;
int sabres_scanned;
/* The APB bridge speaks to the Sabre host PCI bridge
}
once++;
- cookie = alloc_bridge_cookie(&p->pbm_A);
-
- sabre_bus = pci_scan_bus(p->pci_first_busno,
- p->pci_ops,
- &p->pbm_A);
- pci_fixup_host_bridge_self(sabre_bus);
- sabre_bus->self->sysdata = cookie;
+ sabre_bus = pci_scan_one_pbm(&p->pbm_A);
+ if (!sabre_bus)
+ return;
sabre_root_bus = sabre_bus;
} else
continue;
- cookie = alloc_bridge_cookie(pbm);
- pbus->self->sysdata = cookie;
-
sabres_scanned++;
-
pbus->sysdata = pbm;
pbm->pci_bus = pbus;
- pci_fill_in_pbm_cookies(pbus, pbm, pbm->prom_node);
- pci_record_assignments(pbm, pbus);
- pci_assign_unassigned(pbm, pbus);
- pci_fixup_irq(pbm, pbus);
- pci_determine_66mhz_disposition(pbm, pbus);
- pci_setup_busmastering(pbm, pbus);
}
if (!sabres_scanned) {
pbm = &p->pbm_A;
sabre_bus->sysdata = pbm;
pbm->pci_bus = sabre_bus;
- pci_fill_in_pbm_cookies(sabre_bus, pbm, pbm->prom_node);
- pci_record_assignments(pbm, sabre_bus);
- pci_assign_unassigned(pbm, sabre_bus);
- pci_fixup_irq(pbm, sabre_bus);
- pci_determine_66mhz_disposition(pbm, sabre_bus);
- pci_setup_busmastering(pbm, sabre_bus);
}
sabre_register_error_handlers(p);
static void pbm_scan_bus(struct pci_controller_info *p,
struct pci_pbm_info *pbm)
{
- struct pcidev_cookie *cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
-
- if (!cookie) {
- prom_printf("%s: Critical allocation failure.\n", pbm->name);
- prom_halt();
- }
-
- /* All we care about is the PBM. */
- cookie->pbm = pbm;
-
- pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno,
- p->pci_ops,
- pbm);
- pci_fixup_host_bridge_self(pbm->pci_bus);
- pbm->pci_bus->self->sysdata = cookie;
-
- pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
- pci_record_assignments(pbm, pbm->pci_bus);
- pci_assign_unassigned(pbm, pbm->pci_bus);
- pci_fixup_irq(pbm, pbm->pci_bus);
- pci_determine_66mhz_disposition(pbm, pbm->pci_bus);
- pci_setup_busmastering(pbm, pbm->pci_bus);
+ pbm->pci_bus = pci_scan_one_pbm(pbm);
}
static void __schizo_scan_bus(struct pci_controller_info *p,
static void schizo_base_address_update(struct pci_dev *pdev, int resource)
{
- struct pcidev_cookie *pcp = pdev->sysdata;
- struct pci_pbm_info *pbm = pcp->pbm;
+ struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
struct resource *res, *root;
u32 reg;
int where, size, is_64bit;
/* Interrupts must be disabled. */
static long pci_iommu_batch_flush(struct pci_iommu_batch *p)
{
- struct pcidev_cookie *pcp = p->pdev->sysdata;
- unsigned long devhandle = pcp->pbm->devhandle;
+ struct pci_pbm_info *pbm = p->pdev->dev.archdata.host_controller;
+ unsigned long devhandle = pbm->devhandle;
unsigned long prot = p->prot;
unsigned long entry = p->entry;
u64 *pglist = p->pglist;
static void *pci_4v_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp, gfp_t gfp)
{
- struct pcidev_cookie *pcp;
struct pci_iommu *iommu;
unsigned long flags, order, first_page, npages, n;
void *ret;
memset((char *)first_page, 0, PAGE_SIZE << order);
- pcp = pdev->sysdata;
- iommu = pcp->pbm->iommu;
+ iommu = pdev->dev.archdata.iommu;
spin_lock_irqsave(&iommu->lock, flags);
entry = pci_arena_alloc(&iommu->arena, npages);
static void pci_4v_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
{
- struct pcidev_cookie *pcp;
+ struct pci_pbm_info *pbm;
struct pci_iommu *iommu;
unsigned long flags, order, npages, entry;
u32 devhandle;
npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
- pcp = pdev->sysdata;
- iommu = pcp->pbm->iommu;
- devhandle = pcp->pbm->devhandle;
+ iommu = pdev->dev.archdata.iommu;
+ pbm = pdev->dev.archdata.host_controller;
+ devhandle = pbm->devhandle;
entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
spin_lock_irqsave(&iommu->lock, flags);
static dma_addr_t pci_4v_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
{
- struct pcidev_cookie *pcp;
struct pci_iommu *iommu;
unsigned long flags, npages, oaddr;
unsigned long i, base_paddr;
unsigned long prot;
long entry;
- pcp = pdev->sysdata;
- iommu = pcp->pbm->iommu;
+ iommu = pdev->dev.archdata.iommu;
if (unlikely(direction == PCI_DMA_NONE))
goto bad;
static void pci_4v_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
{
- struct pcidev_cookie *pcp;
+ struct pci_pbm_info *pbm;
struct pci_iommu *iommu;
unsigned long flags, npages;
long entry;
return;
}
- pcp = pdev->sysdata;
- iommu = pcp->pbm->iommu;
- devhandle = pcp->pbm->devhandle;
+ iommu = pdev->dev.archdata.iommu;
+ pbm = pdev->dev.archdata.host_controller;
+ devhandle = pbm->devhandle;
npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
npages >>= IO_PAGE_SHIFT;
static int pci_4v_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
{
- struct pcidev_cookie *pcp;
struct pci_iommu *iommu;
unsigned long flags, npages, prot;
u32 dma_base;
return 1;
}
- pcp = pdev->sysdata;
- iommu = pcp->pbm->iommu;
+ iommu = pdev->dev.archdata.iommu;
if (unlikely(direction == PCI_DMA_NONE))
goto bad;
static void pci_4v_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
{
- struct pcidev_cookie *pcp;
+ struct pci_pbm_info *pbm;
struct pci_iommu *iommu;
unsigned long flags, i, npages;
long entry;
WARN_ON(1);
}
- pcp = pdev->sysdata;
- iommu = pcp->pbm->iommu;
- devhandle = pcp->pbm->devhandle;
+ iommu = pdev->dev.archdata.iommu;
+ pbm = pdev->dev.archdata.host_controller;
+ devhandle = pbm->devhandle;
bus_addr = sglist->dma_address & IO_PAGE_MASK;
.dma_sync_sg_for_cpu = pci_4v_dma_sync_sg_for_cpu,
};
-/* SUN4V PCI configuration space accessors. */
-
-struct pdev_entry {
- struct pdev_entry *next;
- u32 devhandle;
- unsigned int bus;
- unsigned int device;
- unsigned int func;
-};
-
-#define PDEV_HTAB_SIZE 16
-#define PDEV_HTAB_MASK (PDEV_HTAB_SIZE - 1)
-static struct pdev_entry *pdev_htab[PDEV_HTAB_SIZE];
-
-static inline unsigned int pdev_hashfn(u32 devhandle, unsigned int bus, unsigned int device, unsigned int func)
-{
- unsigned int val;
-
- val = (devhandle ^ (devhandle >> 4));
- val ^= bus;
- val ^= device;
- val ^= func;
-
- return val & PDEV_HTAB_MASK;
-}
-
-static int pdev_htab_add(u32 devhandle, unsigned int bus, unsigned int device, unsigned int func)
-{
- struct pdev_entry *p = kmalloc(sizeof(*p), GFP_KERNEL);
- struct pdev_entry **slot;
-
- if (!p)
- return -ENOMEM;
-
- slot = &pdev_htab[pdev_hashfn(devhandle, bus, device, func)];
- p->next = *slot;
- *slot = p;
-
- p->devhandle = devhandle;
- p->bus = bus;
- p->device = device;
- p->func = func;
-
- return 0;
-}
-
-/* Recursively descend into the OBP device tree, rooted at toplevel_node,
- * looking for a PCI device matching bus and devfn.
- */
-static int obp_find(struct device_node *toplevel_node, unsigned int bus, unsigned int devfn)
-{
- toplevel_node = toplevel_node->child;
-
- while (toplevel_node != NULL) {
- struct linux_prom_pci_registers *regs;
- struct property *prop;
- int ret;
-
- ret = obp_find(toplevel_node, bus, devfn);
- if (ret != 0)
- return ret;
-
- prop = of_find_property(toplevel_node, "reg", NULL);
- if (!prop)
- goto next_sibling;
-
- regs = prop->value;
- if (((regs->phys_hi >> 16) & 0xff) == bus &&
- ((regs->phys_hi >> 8) & 0xff) == devfn)
- break;
-
- next_sibling:
- toplevel_node = toplevel_node->sibling;
- }
-
- return toplevel_node != NULL;
-}
-
-static int pdev_htab_populate(struct pci_pbm_info *pbm)
-{
- u32 devhandle = pbm->devhandle;
- unsigned int bus;
-
- for (bus = pbm->pci_first_busno; bus <= pbm->pci_last_busno; bus++) {
- unsigned int devfn;
-
- for (devfn = 0; devfn < 256; devfn++) {
- unsigned int device = PCI_SLOT(devfn);
- unsigned int func = PCI_FUNC(devfn);
-
- if (obp_find(pbm->prom_node, bus, devfn)) {
- int err = pdev_htab_add(devhandle, bus,
- device, func);
- if (err)
- return err;
- }
- }
- }
-
- return 0;
-}
-
-static struct pdev_entry *pdev_find(u32 devhandle, unsigned int bus, unsigned int device, unsigned int func)
-{
- struct pdev_entry *p;
-
- p = pdev_htab[pdev_hashfn(devhandle, bus, device, func)];
- while (p) {
- if (p->devhandle == devhandle &&
- p->bus == bus &&
- p->device == device &&
- p->func == func)
- break;
-
- p = p->next;
- }
-
- return p;
-}
-
static inline int pci_sun4v_out_of_range(struct pci_pbm_info *pbm, unsigned int bus, unsigned int device, unsigned int func)
{
if (bus < pbm->pci_first_busno ||
bus > pbm->pci_last_busno)
return 1;
- return pdev_find(pbm->devhandle, bus, device, func) == NULL;
+ return 0;
}
static int pci_sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
static void pbm_scan_bus(struct pci_controller_info *p,
struct pci_pbm_info *pbm)
{
- struct pcidev_cookie *cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
-
- if (!cookie) {
- prom_printf("%s: Critical allocation failure.\n", pbm->name);
- prom_halt();
- }
-
- /* All we care about is the PBM. */
- cookie->pbm = pbm;
-
- pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, p->pci_ops, pbm);
-#if 0
- pci_fixup_host_bridge_self(pbm->pci_bus);
- pbm->pci_bus->self->sysdata = cookie;
-#endif
- pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
- pci_record_assignments(pbm, pbm->pci_bus);
- pci_assign_unassigned(pbm, pbm->pci_bus);
- pci_fixup_irq(pbm, pbm->pci_bus);
- pci_determine_66mhz_disposition(pbm, pbm->pci_bus);
- pci_setup_busmastering(pbm, pbm->pci_bus);
+ pbm->pci_bus = pci_scan_one_pbm(pbm);
}
static void pci_sun4v_scan_bus(struct pci_controller_info *p)
static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource)
{
- struct pcidev_cookie *pcp = pdev->sysdata;
- struct pci_pbm_info *pbm = pcp->pbm;
+ struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
struct resource *res, *root;
u32 reg;
int where, size, is_64bit;
struct pci_dev *pdev,
struct msi_desc *entry)
{
- struct pcidev_cookie *pcp = pdev->sysdata;
- struct pci_pbm_info *pbm = pcp->pbm;
+ struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
unsigned long devino, msiqid;
struct msi_msg msg;
int msi_num, err;
if (pci_sun4v_msi_setvalid(pbm->devhandle, msi_num, HV_MSIVALID_VALID))
goto out_err;
- pcp->msi_num = msi_num;
+ pdev->dev.archdata.msi_num = msi_num;
if (entry->msi_attrib.is_64) {
msg.address_hi = pbm->msi64_start >> 32;
static void pci_sun4v_teardown_msi_irq(unsigned int virt_irq,
struct pci_dev *pdev)
{
- struct pcidev_cookie *pcp = pdev->sysdata;
- struct pci_pbm_info *pbm = pcp->pbm;
+ struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
unsigned long msiqid, err;
unsigned int msi_num;
- msi_num = pcp->msi_num;
+ msi_num = pdev->dev.archdata.msi_num;
err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi_num, &msiqid);
if (err) {
printk(KERN_ERR "%s: getmsiq gives error %lu\n",
pci_sun4v_get_bus_range(pbm);
pci_sun4v_iommu_init(pbm);
pci_sun4v_msi_init(pbm);
-
- pdev_htab_populate(pbm);
}
void sun4v_pci_init(struct device_node *dp, char *model_name)
*
* This file is released under the GPLv2
*/
-#include <asm-generic/device.h>
+#ifndef _ASM_SPARC64_DEVICE_H
+#define _ASM_SPARC64_DEVICE_H
+struct device_node;
+struct of_device;
+
+struct dev_archdata {
+ void *iommu;
+ void *stc;
+ void *host_controller;
+
+ struct device_node *prom_node;
+ struct of_device *op;
+
+ unsigned int msi_num;
+};
+
+#endif /* _ASM_SPARC64_DEVICE_H */
unsigned int pci_last_busno;
};
-/* PCI devices which are not bridges have this placed in their pci_dev
- * sysdata member. This makes OBP aware PCI device drivers easier to
- * code.
- */
-struct pcidev_cookie {
- struct pci_pbm_info *pbm;
- struct device_node *prom_node;
- struct of_device *op;
- struct linux_prom_pci_registers prom_regs[PROMREG_MAX];
- int num_prom_regs;
- struct linux_prom_pci_registers prom_assignments[PROMREG_MAX];
- int num_prom_assignments;
-#ifdef CONFIG_PCI_MSI
- unsigned int msi_num;
-#endif
-};
-
-/* Currently these are the same across all PCI controllers
- * we support. Someday they may not be...
- */
-#define PCI_IRQ_IGN 0x000007c0 /* Interrupt Group Number */
-#define PCI_IRQ_INO 0x0000003f /* Interrupt Number */
-
#endif /* !(__SPARC64_PBM_H) */
projects / GitHub / moto-9609 / android_kernel_motorola_exynos9610.git / commitdiff