[NISTC_DIO_CTRL_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
[NISTC_AI_MODE1_REG] = { 0x118, 2 },
[NISTC_AI_MODE2_REG] = { 0x11a, 2 },
- [AI_SI_Load_A_Registers] = { 0x11c, 4 },
- [AI_SI_Load_B_Registers] = { 0x120, 4 },
- [AI_SC_Load_A_Registers] = { 0x124, 4 },
- [AI_SC_Load_B_Registers] = { 0x128, 4 },
- [AI_SI2_Load_A_Register] = { 0x12c, 4 },
- [AI_SI2_Load_B_Register] = { 0x130, 4 },
+ [NISTC_AI_SI_LOADA_REG] = { 0x11c, 4 },
+ [NISTC_AI_SI_LOADB_REG] = { 0x120, 4 },
+ [NISTC_AI_SC_LOADA_REG] = { 0x124, 4 },
+ [NISTC_AI_SC_LOADB_REG] = { 0x128, 4 },
+ [NISTC_AI_SI2_LOADA_REG] = { 0x12c, 4 },
+ [NISTC_AI_SI2_LOADB_REG] = { 0x130, 4 },
[G_Mode_Register(0)] = { 0x134, 2 },
[G_Mode_Register(1)] = { 0x136, 2 },
[G_Load_A_Register(0)] = { 0x138, 4 },
stop_count += num_adc_stages_611x;
}
/* stage number of scans */
- ni_stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
+ ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
mode1 |= NISTC_AI_MODE1_START_STOP |
NISTC_AI_MODE1_RSVD |
break;
case TRIG_NONE:
/* stage number of scans */
- ni_stc_writel(dev, 0, AI_SC_Load_A_Registers);
+ ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
mode1 |= NISTC_AI_MODE1_START_STOP |
NISTC_AI_MODE1_RSVD |
/* load SI */
timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
CMDF_ROUND_NEAREST);
- ni_stc_writel(dev, timer, AI_SI_Load_A_Registers);
+ ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
break;
case TRIG_EXT:
timer = ni_ns_to_timer(dev, cmd->convert_arg,
CMDF_ROUND_NEAREST);
/* 0,0 does not work */
- ni_stc_writew(dev, 1, AI_SI2_Load_A_Register);
- ni_stc_writew(dev, timer, AI_SI2_Load_B_Register);
+ ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
+ ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* A */
mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
#define NISTC_AI_MODE2_SC_RELOAD_MODE BIT(1)
#define NISTC_AI_MODE2_SC_WR_SWITCH BIT(0)
+#define NISTC_AI_SI_LOADA_REG 14
+#define NISTC_AI_SI_LOADB_REG 16
+#define NISTC_AI_SC_LOADA_REG 18
+#define NISTC_AI_SC_LOADB_REG 20
+#define NISTC_AI_SI2_LOADA_REG 23
+#define NISTC_AI_SI2_LOADB_REG 25
+
#define AI_Status_1_Register 2
#define Interrupt_A_St 0x8000
#define AI_FIFO_Full_St 0x4000
#define DIO_Parallel_Input_Register 7
-#define AI_SI_Load_A_Registers 14
-#define AI_SI_Load_B_Registers 16
-#define AI_SC_Load_A_Registers 18
-#define AI_SC_Load_B_Registers 20
#define AI_SI_Save_Registers 64
#define AI_SC_Save_Registers 66
-#define AI_SI2_Load_A_Register 23
-#define AI_SI2_Load_B_Register 25
-
#define Joint_Status_1_Register 27
#define DIO_Serial_IO_In_Progress_St _bit12