ath9k_hw: Fix minimum CTL power for each runtime mode
authorRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Tue, 22 Nov 2011 13:22:00 +0000 (18:52 +0530)
committerJohn W. Linville <linville@tuxdriver.com>
Mon, 28 Nov 2011 19:36:22 +0000 (14:36 -0500)
The conformance test limits (CTL) for each regulatory domains
(FCC/ETSI/MKK) are programmed for each runtime modes (11B,11G,
HT20 and HT40) in EEPROM. The lowest ctledge power value of a
particular running mode should not be used while computing
ctledge power for a different running mode.(i.e 11G's min ctledge
power should not be used while computing ctledge power for HT20).

Currently, the code does not handle this properly which would
result in incorrect txpowers in certain cases. So reset the
twiceMaxEdgePower to the default while computing min ctlegepower
for every mode.

Cc: David Quan <dquan@qca.qualcomm.com>
Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
drivers/net/wireless/ath/ath9k/eeprom_4k.c
drivers/net/wireless/ath/ath9k/eeprom_9287.c
drivers/net/wireless/ath/ath9k/eeprom_def.c

index a93bd63ad23bd8834f91fb9af42b76543ec8d666..4ba6f52943a86e3659731a7c1b81a9edb745556d 100644 (file)
@@ -4779,7 +4779,7 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
 {
        struct ath_common *common = ath9k_hw_common(ah);
        struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
-       u16 twiceMaxEdgePower = MAX_RATE_POWER;
+       u16 twiceMaxEdgePower;
        int i;
        u16 scaledPower = 0, minCtlPower;
        static const u16 ctlModesFor11a[] = {
@@ -4880,6 +4880,7 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
                        ctlNum = AR9300_NUM_CTLS_5G;
                }
 
+               twiceMaxEdgePower = MAX_RATE_POWER;
                for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
                        ath_dbg(common, ATH_DBG_REGULATORY,
                                "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
index 9a7520f987f0f947747201790d7b125b0d3c232d..61fcab0e2d7650acc598288d8b405011f3e23f04 100644 (file)
@@ -473,7 +473,7 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
 
        int i;
        u16 twiceMinEdgePower;
-       u16 twiceMaxEdgePower = MAX_RATE_POWER;
+       u16 twiceMaxEdgePower;
        u16 scaledPower = 0, minCtlPower;
        u16 numCtlModes;
        const u16 *pCtlMode;
@@ -542,9 +542,7 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
                else
                        freq = centers.ctl_center;
 
-               if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
-                   ah->eep_ops->get_eeprom_rev(ah) <= 2)
-                       twiceMaxEdgePower = MAX_RATE_POWER;
+               twiceMaxEdgePower = MAX_RATE_POWER;
 
                for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
                             pEepData->ctlIndex[i]; i++) {
index 4f5c50a87ce345bb49de09315f7aae74bc03e7fb..0981c073471de9f0b1469b660c1e4993f45aeb96 100644 (file)
@@ -569,7 +569,7 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN     6
 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   10
 
-       u16 twiceMaxEdgePower = MAX_RATE_POWER;
+       u16 twiceMaxEdgePower;
        int i;
        struct cal_ctl_data_ar9287 *rep;
        struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} },
@@ -669,6 +669,7 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
                else
                        freq = centers.ctl_center;
 
+               twiceMaxEdgePower = MAX_RATE_POWER;
                /* Walk through the CTL indices stored in EEPROM */
                for (i = 0; (i < AR9287_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
                        struct cal_ctl_edges *pRdEdgesPower;
index 81e6296716794490ca1073613d5bec8497a85820..55a21d39167c06d9dc86c24253c89f318062481d 100644 (file)
@@ -1000,7 +1000,7 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   9 /* 10*log10(3)*2 */
 
        struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
-       u16 twiceMaxEdgePower = MAX_RATE_POWER;
+       u16 twiceMaxEdgePower;
        int i;
        struct cal_ctl_data *rep;
        struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
@@ -1121,9 +1121,7 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
                else
                        freq = centers.ctl_center;
 
-               if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
-                   ah->eep_ops->get_eeprom_rev(ah) <= 2)
-                       twiceMaxEdgePower = MAX_RATE_POWER;
+               twiceMaxEdgePower = MAX_RATE_POWER;
 
                for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
                        if ((((cfgCtl & ~CTL_MODE_M) |