ARM: dts: dra7x-evm: Provide NAND ready pin
authorRoger Quadros <rogerq@ti.com>
Thu, 7 Apr 2016 10:25:37 +0000 (13:25 +0300)
committerTony Lindgren <tony@atomide.com>
Tue, 12 Apr 2016 21:32:02 +0000 (14:32 -0700)
On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.

Read speed increases from 13768 KiB/ to 17246 KiB/s.
Write speed was unchanged at 7123 KiB/s.
Measured using mtd_speedtest.ko.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/boot/dts/dra7-evm.dts
arch/arm/boot/dts/dra72-evm.dts

index 7fda602868d7c6f4aac2ba789886e08b75dc2d55..d272cf14019780cb4a1b2c053308c3cdd6b25468 100644 (file)
                interrupt-parent = <&gpmc>;
                interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                             <1 IRQ_TYPE_NONE>; /* termcount */
+               rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
                ti,nand-ecc-opt = "bch8";
                ti,elm-id = <&elm>;
                nand-bus-width = <16>;
index 4bd639b9ff919ba2000a5b9926fbca7977c960ea..3e63f660cd7c47b144b1c8ee599717ccbad08133 100644 (file)
                interrupt-parent = <&gpmc>;
                interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                             <1 IRQ_TYPE_NONE>; /* termcount */
+               rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
                ti,nand-ecc-opt = "bch8";
                ti,elm-id = <&elm>;
                nand-bus-width = <16>;