static const struct mio_regmap m_series_stc_write_regmap[] = {
[NISTC_INTA_ACK_REG] = { 0x104, 2 },
[NISTC_INTB_ACK_REG] = { 0x106, 2 },
- [AI_Command_2_Register] = { 0x108, 2 },
+ [NISTC_AI_CMD2_REG] = { 0x108, 2 },
[AO_Command_2_Register] = { 0x10a, 2 },
[G_Command_Register(0)] = { 0x10c, 2 },
[G_Command_Register(1)] = { 0x10e, 2 },
s->async->events |= COMEDI_CB_EOS;
#endif
}
- /* handle special case of single scan using AI_End_On_End_Of_Scan */
- if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan))
+ /* handle special case of single scan */
+ if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
shutdown_ai_command(dev);
}
if (trig_num != cmd->start_arg)
return -EINVAL;
- ni_stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
- AI_Command_2_Register);
+ ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
+ NISTC_AI_CMD2_REG);
s->async->inttrig = NULL;
return 1;
ni_stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
if (stop_count == 0) {
- devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
+ devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
interrupt_a_enable |= AI_STOP_Interrupt_Enable;
/* this is required to get the last sample for chanlist_len > 1, not sure why */
if (cmd->chanlist_len > 1)
interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
#endif
- if (cmd->flags & CMDF_WAKE_EOS
- || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
+ if ((cmd->flags & CMDF_WAKE_EOS) ||
+ (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
/* wake on end-of-scan */
devpriv->aimode = AIMODE_SCAN;
} else {
#endif
if (cmd->start_src == TRIG_NOW) {
- /* AI_START1_Pulse */
- ni_stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
- AI_Command_2_Register);
+ ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
+ devpriv->ai_cmd2,
+ NISTC_AI_CMD2_REG);
s->async->inttrig = NULL;
} else if (cmd->start_src == TRIG_EXT) {
s->async->inttrig = NULL;
NISTC_INTB_ACK_AO_BC_TC_ERR | \
NISTC_INTB_ACK_AO_BC_TC_TRIG_ERR)
+#define NISTC_AI_CMD2_REG 4
+#define NISTC_AI_CMD2_END_ON_SC_TC BIT(15)
+#define NISTC_AI_CMD2_END_ON_EOS BIT(14)
+#define NISTC_AI_CMD2_START1_DISABLE BIT(11)
+#define NISTC_AI_CMD2_SC_SAVE_TRACE BIT(10)
+#define NISTC_AI_CMD2_SI_SW_ON_SC_TC BIT(9)
+#define NISTC_AI_CMD2_SI_SW_ON_STOP BIT(8)
+#define NISTC_AI_CMD2_SI_SW_ON_TC BIT(7)
+#define NISTC_AI_CMD2_SC_SW_ON_TC BIT(4)
+#define NISTC_AI_CMD2_STOP_PULSE BIT(3)
+#define NISTC_AI_CMD2_START_PULSE BIT(2)
+#define NISTC_AI_CMD2_START2_PULSE BIT(1)
+#define NISTC_AI_CMD2_START1_PULSE BIT(0)
+
#define AI_Status_1_Register 2
#define Interrupt_A_St 0x8000
#define AI_FIFO_Full_St 0x4000
#define AO_FIFO_Request_St _bit1
#define Pass_Thru_1_Interrupt_St _bit0
-#define AI_Command_2_Register 4
-#define AI_End_On_SC_TC _bit15
-#define AI_End_On_End_Of_Scan _bit14
-#define AI_START1_Disable _bit11
-#define AI_SC_Save_Trace _bit10
-#define AI_SI_Switch_Load_On_SC_TC _bit9
-#define AI_SI_Switch_Load_On_STOP _bit8
-#define AI_SI_Switch_Load_On_TC _bit7
-#define AI_SC_Switch_Load_On_TC _bit4
-#define AI_STOP_Pulse _bit3
-#define AI_START_Pulse _bit2
-#define AI_START2_Pulse _bit1
-#define AI_START1_Pulse _bit0
-
#define AO_Command_2_Register 5
#define AO_End_On_BC_TC(x) (((x) & 0x3) << 14)
#define AO_Start_Stop_Gate_Enable _bit13