MIPS: Netlogic: Add default DTB for XLP9XX SoC
authorJayachandran C <jchandra@broadcom.com>
Sat, 21 Dec 2013 11:22:30 +0000 (16:52 +0530)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 24 Jan 2014 21:39:50 +0000 (22:39 +0100)
Add a default device tree fie for XLP9XX boards, and add code to use
this device tree if no DTB is passed to the kernel.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6287/

arch/mips/netlogic/Kconfig
arch/mips/netlogic/dts/Makefile
arch/mips/netlogic/dts/xlp_gvp.dts [new file with mode: 0644]
arch/mips/netlogic/xlp/dt.c

index 852a4ee09954dacd635a2cfe6827b56bcd48acdc..4eb683aef7d7669bf86cae46a45b5c352fbfab39 100644 (file)
@@ -28,6 +28,15 @@ config DT_XLP_FVP
          pointer to the kernel.  The corresponding DTS file is at
          arch/mips/netlogic/dts/xlp_fvp.dts
 
+config DT_XLP_GVP
+       bool "Built-in device tree for XLP GVP boards"
+       default y
+       help
+         Add an FDT blob for XLP GVP board into the kernel.
+         This DTB will be used if the firmware does not pass in a DTB
+         pointer to the kernel.  The corresponding DTS file is at
+         arch/mips/netlogic/dts/xlp_gvp.dts
+
 config NLM_MULTINODE
        bool "Support for multi-chip boards"
        depends on NLM_XLP_BOARD
index 0b9be5fd2e466e771ec51ec40a7f1ffeae0a8e47..25c8e873ee2577464f47f2475c1c26704341899f 100644 (file)
@@ -1,3 +1,4 @@
 obj-$(CONFIG_DT_XLP_EVP) := xlp_evp.dtb.o
 obj-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb.o
 obj-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb.o
+obj-$(CONFIG_DT_XLP_GVP) += xlp_gvp.dtb.o
diff --git a/arch/mips/netlogic/dts/xlp_gvp.dts b/arch/mips/netlogic/dts/xlp_gvp.dts
new file mode 100644 (file)
index 0000000..047d27f
--- /dev/null
@@ -0,0 +1,76 @@
+/*
+ * XLP9XX Device Tree Source for GVP boards
+ */
+
+/dts-v1/;
+/ {
+       model = "netlogic,XLP-GVP";
+       compatible = "netlogic,xlp";
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       soc {
+               #address-cells = <2>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               ranges = <0 0  0 0x18000000  0x04000000   // PCIe CFG
+                         1 0  0 0x16000000  0x02000000>; // GBU chipselects
+
+               serial0: serial@30000 {
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <0 0x112100 0xa00>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clock-frequency = <125000000>;
+                       interrupt-parent = <&pic>;
+                       interrupts = <17>;
+               };
+               pic: pic@4000 {
+                       interrupt-controller;
+                       #address-cells = <0>;
+                       #interrupt-cells = <1>;
+                       reg = <0 0x110000 0x200>;
+               };
+
+               nor_flash@1,0 {
+                       compatible = "cfi-flash";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       bank-width = <2>;
+                       reg = <1 0 0x1000000>;
+
+                       partition@0 {
+                               label = "x-loader";
+                               reg = <0x0 0x100000>; /* 1M */
+                               read-only;
+                       };
+
+                       partition@100000 {
+                               label = "u-boot";
+                               reg = <0x100000 0x100000>; /* 1M */
+                       };
+
+                       partition@200000 {
+                               label = "kernel";
+                               reg = <0x200000 0x500000>; /* 5M */
+                       };
+
+                       partition@700000 {
+                               label = "rootfs";
+                               reg = <0x700000 0x800000>; /* 8M */
+                       };
+
+                       partition@f00000 {
+                               label = "env";
+                               reg = <0xf00000 0x100000>; /* 1M */
+                               read-only;
+                       };
+               };
+
+       };
+
+       chosen {
+               bootargs = "console=ttyS0,115200 rdinit=/sbin/init";
+       };
+};
index 8316d5454b1751d8f65e5f63a1017e198ce0bc31..5754097b9cde83d5a57ab86c67eda7ee0c35e528 100644 (file)
 #include <asm/prom.h>
 
 extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[],
-       __dtb_xlp_fvp_begin[], __dtb_start[];
+       __dtb_xlp_fvp_begin[], __dtb_xlp_gvp_begin[], __dtb_start[];
 static void *xlp_fdt_blob;
 
 void __init *xlp_dt_init(void *fdtp)
 {
        if (!fdtp) {
                switch (current_cpu_data.processor_id & 0xff00) {
+#ifdef CONFIG_DT_XLP_GVP
+               case PRID_IMP_NETLOGIC_XLP9XX:
+                       fdtp = __dtb_xlp_gvp_begin;
+                       break;
+#endif
 #ifdef CONFIG_DT_XLP_FVP
                case PRID_IMP_NETLOGIC_XLP2XX:
                        fdtp = __dtb_xlp_fvp_begin;