perf, x86: add some IBS macros to perf_event.h

Signed-off-by: Robert Richter <robert.richter@amd.com>

diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 4933ccde96c4c884655f92219c3e2ab2c43f1070..c7f60e1297ab5c82e859a62188942f352e47e3d6 100644 (file)
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -121,12 +121,14 @@ union cpuid10_edx {
 #define IBS_FETCH_RAND_EN              (1ULL<<57)
 #define IBS_FETCH_VAL                  (1ULL<<49)
 #define IBS_FETCH_ENABLE               (1ULL<<48)
-#define IBS_FETCH_CNT_MASK             0xFFFF0000ULL
+#define IBS_FETCH_CNT                  0xFFFF0000ULL
+#define IBS_FETCH_MAX_CNT              0x0000FFFFULL
 
 /* IbsOpCtl bits */
 #define IBS_OP_CNT_CTL                 (1ULL<<19)
 #define IBS_OP_VAL                     (1ULL<<18)
 #define IBS_OP_ENABLE                  (1ULL<<17)
+#define IBS_OP_MAX_CNT                 0x0000FFFFULL
 
 #ifdef CONFIG_PERF_EVENTS
 extern void init_hw_perf_events(void);

diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c
index c67174917305420f2d607b62be302b3908103208..8ddb9fa9c1b2d2fb26413225b1e09daf6b854b8b 100644 (file)
--- a/arch/x86/oprofile/op_model_amd.c
+++ b/arch/x86/oprofile/op_model_amd.c
@@ -279,7 +279,7 @@ op_amd_handle_ibs(struct pt_regs * const regs,
                        oprofile_write_commit(&entry);
 
                        /* reenable the IRQ */
-                       ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT_MASK);
+                       ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT);
                        ctl |= IBS_FETCH_ENABLE;
                        wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
                }
@@ -319,7 +319,7 @@ static inline void op_amd_start_ibs(void)
                return;
 
        if (ibs_config.fetch_enabled) {
-               val = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
+               val = (ibs_config.max_cnt_fetch >> 4) & IBS_FETCH_MAX_CNT;
                val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
                val |= IBS_FETCH_ENABLE;
                wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
@@ -341,7 +341,7 @@ static inline void op_amd_start_ibs(void)
                         * avoid underflows.
                         */
                        ibs_op_ctl = min(ibs_op_ctl + IBS_RANDOM_MAXCNT_OFFSET,
-                                        0xFFFFULL);
+                                        IBS_OP_MAX_CNT);
                }
                if (ibs_caps & IBS_CAPS_OPCNT && ibs_config.dispatched_ops)
                        ibs_op_ctl |= IBS_OP_CNT_CTL;