m68knommu: create bit definitions for the version 2 ColdFire cache controller

The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index aa7ee48d505938a359655f1e1ee478f11bfa4acb..561b03b5ddf8474b6b231c4b1233d720d5cc31e2 100644 (file)
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -15,6 +15,8 @@
 #define        CPU_NAME                "COLDFIRE(m5206)"
 #define        CPU_INSTR_PER_JIFFY     3
 
+#include <asm/m52xxacr.h>
+
 /*
  *     Define the 5206 SIM register set addresses.
  */

diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index 8cd8bce38594026268577543c06b7b5e193a1d4d..88ed8239fe4ec9517f79d8285a87f3932cf6de06 100644 (file)
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -14,6 +14,8 @@
 #define        CPU_NAME                "COLDFIRE(m520x)"
 #define        CPU_INSTR_PER_JIFFY     3
 
+#include <asm/m52xxacr.h>
+
 /*
  *  Define the 520x SIM register set addresses.
  */
@@ -57,6 +59,9 @@
 #define MCFSIM_SDCS0        0x000a8110 /* SDRAM Chip Select 0 Configuration */
 #define MCFSIM_SDCS1        0x000a8114 /* SDRAM Chip Select 1 Configuration */
 
+/*
+ * EPORT and GPIO registers.
+ */
 #define MCFEPORT_EPDDR                 0xFC088002
 #define MCFEPORT_EPDR                  0xFC088004
 #define MCFEPORT_EPPDR                 0xFC088005

diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 4ec0f93a7ece0cdcc2af1fa1782eadb4cca1ea1a..4ad7a00257a820a1bff3df7946873e62cc56fed7 100644 (file)
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -14,6 +14,8 @@
 #define        CPU_NAME                "COLDFIRE(m523x)"
 #define        CPU_INSTR_PER_JIFFY     3
 
+#include <asm/m52xxacr.h>
+
 /*
  *     Define the 523x SIM register set addresses.
  */

diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 21d0bbfbc0c9c34c7b5dab42304ef2b0b475c250..4908b118f2fd507d4eb648233816e235ae3234f5 100644 (file)
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -14,6 +14,8 @@
 #define        CPU_NAME                "COLDFIRE(m5249)"
 #define        CPU_INSTR_PER_JIFFY     3
 
+#include <asm/m52xxacr.h>
+
 /*
  *     Define the 5249 SIM register set addresses.
  */

diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index 974c448c098e0915d2616165fd7d8cae67ca7801..b7cc50abc8315e3f677c4a54e0d576b8d1709514 100644 (file)
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -15,6 +15,8 @@
 #define        CPU_NAME                "COLDFIRE(m5272)"
 #define        CPU_INSTR_PER_JIFFY     3
 
+#include <asm/m52xxacr.h>
+
 /*
  *     Define the 5272 SIM register set addresses.
  */

diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 8a5a1ab57d018855257a39554139d38b8c0d832c..e8042e8bc003fc726f0d6bc106e233e6da309dbe 100644 (file)
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -14,6 +14,7 @@
 #define        CPU_NAME                "COLDFIRE(m527x)"
 #define        CPU_INSTR_PER_JIFFY     3
 
+#include <asm/m52xxacr.h>
 
 /*
  *     Define the 5270/5271 SIM register set addresses.

diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index 47c851ef78d3e717f76be83a7072601b7e705d72..a6d2f4d9aaa059acb55b889f3d1967ad6ed18ef9 100644 (file)
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -14,6 +14,8 @@
 #define        CPU_NAME                "COLDFIRE(m528x)"
 #define        CPU_INSTR_PER_JIFFY     3
 
+#include <asm/m52xxacr.h>
+
 /*
  *     Define the 5280/5282 SIM register set addresses.
  */

diff --git a/arch/m68k/include/asm/m52xxacr.h b/arch/m68k/include/asm/m52xxacr.h
new file mode 100644 (file)
index 0000000..4c92d99
--- /dev/null
+++ b/arch/m68k/include/asm/m52xxacr.h
@@ -0,0 +1,56 @@
+/****************************************************************************/
+
+/*
+ * m52xxacr.h -- ColdFire version 2 core cache support
+ *
+ * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
+ */
+
+/****************************************************************************/
+#ifndef m52xxacr_h
+#define m52xxacr_h
+/****************************************************************************/
+
+/*
+ * All varients of the ColdFire using version 2 cores have a similar
+ * cache setup. Although not absolutely identical the cache register
+ * definitions are compatible for all of them. Mostly they support a
+ * configurable cache memory that can be instruction only, data only,
+ * or split instruction and data. The exception is the very old version 2
+ * core based parts, like the 5206(e), 5249 and 5272, which are instruction
+ * cache only. Cache size varies from 2k up to 16k.
+ */
+
+/*
+ * Define the Cache Control register flags.
+ */
+#define CACR_CENB      0x80000000      /* Enable cache */
+#define CACR_CDPI      0x10000000      /* Disable invalidation by CPUSHL */
+#define CACR_CFRZ      0x08000000      /* Cache freeze mode */
+#define CACR_CINV      0x01000000      /* Invalidate cache */
+#define CACR_DISI      0x00800000      /* Disable instruction cache */
+#define CACR_DISD      0x00400000      /* Disable data cache */
+#define CACR_INVI      0x00200000      /* Invalidate instruction cache */
+#define CACR_INVD      0x00100000      /* Invalidate data cache */
+#define CACR_CEIB      0x00000400      /* Non-cachable instruction burst */
+#define CACR_DCM       0x00000200      /* Default cache mode */
+#define CACR_DBWE      0x00000100      /* Buffered write enable */
+#define CACR_DWP       0x00000020      /* Write protection */
+#define CACR_EUSP      0x00000010      /* Enable separate user a7 */
+
+/*
+ * Define the Access Control register flags.
+ */
+#define ACR_BASE_POS   24              /* Address Base (upper 8 bits) */
+#define ACR_MASK_POS   16              /* Address Mask (next 8 bits) */
+#define ACR_ENABLE     0x00008000      /* Enable this ACR */
+#define ACR_USER       0x00000000      /* Allow only user accesses */
+#define ACR_SUPER      0x00002000      /* Allow supervisor access only */
+#define ACR_ANY                0x00004000      /* Allow any access type */
+#define ACR_CENB       0x00000000      /* Caching of region enabled */
+#define ACR_CDIS       0x00000040      /* Caching of region disabled */
+#define ACR_BWE                0x00000020      /* Write buffer enabled */
+#define ACR_WPROTECT   0x00000004      /* Write protect region */
+
+/****************************************************************************/
+#endif  /* m52xxsim_h */