drm/radeon: fix DMA CS parser for r6xx linear copy packet

Was using the r7xx format.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 9ea13d07cc55c75fbb7df5ffff7865661a526c5f..03191a56eb443424d35ffbaa84b82ffe96fa1d8a 100644 (file)
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -2677,16 +2677,29 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p)
                                }
                                p->idx += 7;
                        } else {
-                               src_offset = ib[idx+2];
-                               src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
-                               dst_offset = ib[idx+1];
-                               dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
+                               if (p->family >= CHIP_RV770) {
+                                       src_offset = ib[idx+2];
+                                       src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
+                                       dst_offset = ib[idx+1];
+                                       dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
 
-                               ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
-                               ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
-                               ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
-                               ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
-                               p->idx += 5;
+                                       ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
+                                       ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
+                                       ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
+                                       ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
+                                       p->idx += 5;
+                               } else {
+                                       src_offset = ib[idx+2];
+                                       src_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
+                                       dst_offset = ib[idx+1];
+                                       dst_offset |= ((u64)(ib[idx+3] & 0xff0000)) << 16;
+
+                                       ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
+                                       ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
+                                       ib[idx+3] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
+                                       ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff) << 16;
+                                       p->idx += 4;
+                               }
                        }
                        if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
                                dev_warn(p->dev, "DMA copy src buffer too small (%llu %lu)\n",