clk: renesas: r8a7796: Add PWM clock

This patch adds PWM clock for PWM.

Signed-off-by: Ryo Kodama <ryo.kodama.vz@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
[geert: Correct parent clock]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 5c95e636a8d6ace9ff6f44023a13dc616d02c8af..ab8ad5e6f53771ce04e3701ccd326b981d18ae34 100644 (file)
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -156,6 +156,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
        DEF_MOD("hscif1",                519,   R8A7796_CLK_S3D1),
        DEF_MOD("hscif0",                520,   R8A7796_CLK_S3D1),
        DEF_MOD("thermal",               522,   R8A7796_CLK_CP),
+       DEF_MOD("pwm",                   523,   R8A7796_CLK_S0D12),
        DEF_MOD("fcpvd2",                601,   R8A7796_CLK_S0D2),
        DEF_MOD("fcpvd1",                602,   R8A7796_CLK_S0D2),
        DEF_MOD("fcpvd0",                603,   R8A7796_CLK_S0D2),