arm: mvebu: add PCIe Device Tree informations for Armada 370
authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tue, 9 Apr 2013 21:06:33 +0000 (23:06 +0200)
committerJason Cooper <jason@lakedaemon.net>
Mon, 15 Apr 2013 14:53:03 +0000 (14:53 +0000)
The Armada 370 SoC has two 1x PCIe 2.0 interfaces, so we add the
necessary Device Tree informations to make these interfaces availabel.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
arch/arm/boot/dts/armada-370.dtsi

index 5831994a311b73a7be2e36393c3776ae3a800967..9cf60b2ce864a17dbc4ab7654c940b40eb695dc2 100644 (file)
                               0xd0018304 0x4>;
                        status = "okay";
                };
+
+               pcie-controller {
+                       compatible = "marvell,armada-370-pcie";
+                       status = "disabled";
+                       device_type = "pci";
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       bus-range = <0x00 0xff>;
+
+                       reg = <0xd0040000 0x2000>, <0xd0080000 0x2000>;
+
+                       reg-names = "pcie0.0", "pcie1.0";
+
+                       ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */
+                                 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000   /* Port 1.0 registers */
+                                 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+                                 0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+
+                       pcie@1,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
+                               reg = <0x0800 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 58>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gateclk 5>;
+                               status = "disabled";
+                       };
+
+                       pcie@2,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
+                               reg = <0x1000 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &mpic 62>;
+                               marvell,pcie-port = <1>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gateclk 9>;
+                               status = "disabled";
+                       };
+               };
        };
 };