* Hardware access
*/
+static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+ void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
+ u8 bit;
+
+ if (bank->bank_type == RK3188_BANK0 && pin < 16)
+ return RK_FUNC_GPIO;
+
+ /* get basic quadrupel of mux registers and the correct reg inside */
+ reg += bank->bank_num * 0x10;
+ reg += (pin / 8) * 4;
+ bit = (pin % 8) * 2;
+
+ return ((readl(reg) >> bit) & 3);
+}
+
/*
* Set a new mux function for a pin.
*
return false;
}
+static int rockchip_gpio_direction_output(struct gpio_chip *gc,
+ unsigned offset, int value);
+static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
+
/* set the pin config settings for a specified pin */
static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned num_configs)
if (rc)
return rc;
break;
+ case PIN_CONFIG_OUTPUT:
+ rc = rockchip_gpio_direction_output(&bank->gpio_chip,
+ pin - bank->pin_base,
+ arg);
+ if (rc)
+ return rc;
+ break;
default:
return -ENOTSUPP;
break;
struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
enum pin_config_param param = pinconf_to_config_param(*config);
u16 arg;
+ int rc;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
arg = 1;
break;
+ case PIN_CONFIG_OUTPUT:
+ rc = rockchip_get_mux(bank, pin - bank->pin_base);
+ if (rc != RK_FUNC_GPIO)
+ return -EINVAL;
+
+ rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
+ if (rc < 0)
+ return rc;
+
+ arg = rc ? 1 : 0;
+ break;
default:
return -ENOTSUPP;
break;