#define XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST \
(XENON_EMMC_5_0_PHY_REG_BASE + 0x14)
+#define XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE 0x5A54
#define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST (XENON_EMMC_PHY_REG_BASE + 0x18)
#define XENON_LOGIC_TIMING_VALUE 0x00AA8977
u16 logic_timing_adj;
/* DLL Update Enable bit */
u32 dll_update;
+ /* value in Logic Timing Adjustment register */
+ u32 logic_timing_val;
};
static const char * const phy_types[] = {
.dll_ctrl = XENON_EMMC_5_0_PHY_DLL_CONTROL,
.logic_timing_adj = XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST,
.dll_update = XENON_DLL_UPDATE_STROBE_5_0,
+ .logic_timing_val = XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE,
};
static struct xenon_emmc_phy_regs xenon_emmc_5_1_phy_regs = {
.dll_ctrl = XENON_EMMC_PHY_DLL_CONTROL,
.logic_timing_adj = XENON_EMMC_PHY_LOGIC_TIMING_ADJUST,
.dll_update = XENON_DLL_UPDATE,
+ .logic_timing_val = XENON_LOGIC_TIMING_VALUE,
};
/*
if (timing == MMC_TIMING_MMC_HS400)
/* Hardware team recommend a value for HS400 */
- sdhci_writel(host, XENON_LOGIC_TIMING_VALUE,
+ sdhci_writel(host, phy_regs->logic_timing_val,
phy_regs->logic_timing_adj);
else
xenon_emmc_phy_disable_data_strobe(host);